arm: mx6: rename some missed instances of CONFIG_MX6* to CONFIG_SOC_MX6*

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / ddr.c

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 37654e0677e8db4c9a81bb806f4b171db1da6933..9080d11764cb8f86c1585809a11f2a4a90682ca7 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -71,6 +71,50 @@ void mx6sx_dram_iocfg(unsigned width,
 }
 #endif
 
+#ifdef CONFIG_SOC_MX6UL
+void mx6ul_dram_iocfg(unsigned width,
+                     const struct mx6ul_iomux_ddr_regs *ddr,
+                     const struct mx6ul_iomux_grp_regs *grp)
+{
+       struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
+       struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
+
+       mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
+       mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
+
+       /* DDR IO TYPE */
+       writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
+       writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
+
+       /* CLOCK */
+       writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
+
+       /* ADDRESS */
+       writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
+       writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
+       writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
+
+       /* Control */
+       writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
+       writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
+       writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
+       writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
+       writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
+
+       /* Data Strobes */
+       writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
+       writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
+       writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
+
+       /* Data */
+       writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
+       writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
+       writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
+       writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
+       writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
+}
+#endif
+
 #if defined(CONFIG_SOC_MX6QDL) || defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D)
 /* Configure MX6DQ mmdc iomux */
 void mx6dq_dram_iocfg(unsigned width,
@@ -243,19 +287,17 @@ void mx6sdl_dram_iocfg(unsigned width,
  */
 #define MR(val, ba, cmd, cs1) \
        ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-#ifdef CONFIG_SOC_MX6SX
-#define MMDC1(entry, value)    do {} while (0)
-#else
-#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
-#endif
+#define MMDC1(entry, value) do {                                         \
+       if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))   \
+               mmdc1->entry = value;                                     \
+       } while (0)
+
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
                  const struct mx6_mmdc_calibration *calib,
                  const struct mx6_ddr3_cfg *ddr3_cfg)
 {
        volatile struct mmdc_p_regs *mmdc0;
-#ifndef CONFIG_SOC_MX6SX
        volatile struct mmdc_p_regs *mmdc1;
-#endif
        u32 val;
        u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
        u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -270,9 +312,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
        u16 mem_speed = ddr3_cfg->mem_speed;
 
        mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-#ifndef CONFIG_SOC_MX6SX
-       mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
-#endif
+       if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
+               mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
        /* Limit mem_speed for MX6D/MX6Q */
        if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
@@ -352,28 +393,6 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
                        trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
                }
                break;
-       case 1333:
-               txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
-               tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
-               if (ddr3_cfg->pagesz == 1) {
-                       tfaw = DIV_ROUND_UP(30000, clkper) - 1;
-                       trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
-               } else {
-                       tfaw = DIV_ROUND_UP(45000, clkper) - 1;
-                       trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
-               }
-               break;
-       case 1600:
-               txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
-               tcke = DIV_ROUND_UP(max(3 * clkper, 5000), clkper) - 1;
-               if (ddr3_cfg->pagesz == 1) {
-                       tfaw = DIV_ROUND_UP(30000, clkper) - 1;
-                       trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
-               } else {
-                       tfaw = DIV_ROUND_UP(40000, clkper) - 1;
-                       trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
-               }
-               break;
        default:
                puts("invalid memory speed\n");
                hang();
@@ -543,7 +562,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
                /* MR0 */
                val = ((tcl - 1) << 4) |        /* CAS */
                      (1 << 8)   |              /* DLL Reset */
-                     ((twr - 3) << 9);         /* Write Recovery */
+                     ((twr - 3) << 9) |        /* Write Recovery */
+                     (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
                debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
                mmdc0->mdscr = MR(val, 0, 3, cs);
                /* ZQ calibration */