mx6: soc: Disable VDDPU regulator

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 3e095aab848d5bc96806c085cdb69a8f987184a4..009a644abf23d50ce1092047e4ca7e9264ab1d2e 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -19,6 +19,14 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 
+#define VDDPU_MASK     (0x1f << 9)
+
+enum ldo_reg {
+       LDO_ARM,
+       LDO_SOC,
+       LDO_PU,
+};
+
 struct scu_regs {
        u32     ctrl;
        u32     config;
@@ -115,10 +123,11 @@ static void clear_ldo_ramp(void)
  * Possible values are from 0.725V to 1.450V in steps of
  * 0.025V (25mV).
  */
-static void set_vddsoc(u32 mv)
+static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-       u32 val, reg = readl(&anatop->reg_core);
+       u32 val, step, old, reg = readl(&anatop->reg_core);
+       u8 shift;
 
        if (mv < 725)
                val = 0x00;     /* Power gated off */
@@ -129,12 +138,35 @@ static void set_vddsoc(u32 mv)
 
        clear_ldo_ramp();
 
+       switch (ldo) {
+       case LDO_SOC:
+               shift = 18;
+               break;
+       case LDO_PU:
+               shift = 9;
+               break;
+       case LDO_ARM:
+               shift = 0;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       old = (reg & (0x1F << shift)) >> shift;
+       step = abs(val - old);
+       if (step == 0)
+               return 0;
+
+       reg = (reg & ~(0x1F << shift)) | (val << shift);
+       writel(reg, &anatop->reg_core);
+
        /*
-        * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
-        * and set them to the calculated value (0.7V + val * 0.25V)
+        * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
+        * step
         */
-       reg = (reg & ~(0x1F << 18)) | (val << 18);
-       writel(reg, &anatop->reg_core);
+       udelay(3 * step);
+
+       return 0;
 }
 
 static void imx_set_wdog_powerdown(bool enable)
@@ -147,13 +179,50 @@ static void imx_set_wdog_powerdown(bool enable)
        writew(enable, &wdog2->wmcr);
 }
 
+static void imx_set_vddpu_power_down(void)
+{
+       struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+       struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
+
+       u32 reg;
+
+       /*
+        * Disable the brown out detection since we are going to be
+        * disabling the LDO.
+        */
+       reg = readl(&anatop->ana_misc2);
+       reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
+       writel(reg, &anatop->ana_misc2);
+
+       /* need to power down xPU in GPC before turning off PU LDO */
+       reg = readl(&gpc->gpu_ctrl);
+       writel(reg | 0x1, &gpc->gpu_ctrl);
+
+       reg = readl(&gpc->ctrl);
+       writel(reg | 0x1, &gpc->ctrl);
+       while (readl(&gpc->ctrl) & 0x1)
+               ;
+
+       /* Mask the ANATOP brown out interrupt in the GPC. */
+       reg = readl(&gpc->imr4);
+       reg |= 0x80000000;
+       writel(reg, &gpc->imr4);
+
+       /* disable VDDPU */
+       writel(VDDPU_MASK, &anatop->reg_core_clr);
+
+       /* Clear the BO interrupt in the ANATOP. */
+       reg = readl(&anatop->ana_misc1);
+       reg |= 0x80000000;
+       writel(reg, &anatop->ana_misc1);
+}
+
 int arch_cpu_init(void)
 {
        init_aips();
 
-       set_vddsoc(1175);       /* Set VDDSOC to 1.175V */
-
        imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+       imx_set_vddpu_power_down();
 
 #ifdef CONFIG_APBH_DMA
        /* Start APBH DMA */
@@ -163,6 +232,13 @@ int arch_cpu_init(void)
        return 0;
 }
 
+int board_postclk_init(void)
+{
+       set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
+
+       return 0;
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {