imx6: ensure AHB clock is 132MHz in low freq boot mode

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 0208cba9cc7a50a08514987db65b33ac9b39c022..33a293941514ac243d9c9b81fb802296a1d766d7 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -177,10 +177,30 @@ static void imx_set_wdog_powerdown(bool enable)
        writew(enable, &wdog2->wmcr);
 }
 
+static void set_ahb_rate(u32 val)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       u32 reg, div;
+
+       div = get_periph_clk() / val - 1;
+       reg = readl(&mxc_ccm->cbcdr);
+
+       writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
+               (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
+}
+
 int arch_cpu_init(void)
 {
        init_aips();
 
+       /*
+        * When low freq boot is enabled, ROM will not set AHB
+        * freq, so we need to ensure AHB freq is 132MHz in such
+        * scenario.
+        */
+       if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+               set_ahb_rate(132000000);
+
        imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
 #ifdef CONFIG_APBH_DMA