i.MX6: Set and clear the gating bits for Phase Fractional Dividers

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 8150bffb8ce60b5c1947f65e5554598b24316f6d..a3902962b5249c4ebf9ef66df991d42b69e007f8 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -213,6 +213,34 @@ const struct boot_mode soc_boot_modes[] = {
 
 void s_init(void)
 {
+       struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+       int is_6q = is_cpu_type(MXC_CPU_MX6Q);
+       u32 mask480;
+       u32 mask528;
+
+       /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
+        * to make sure PFD is working right, otherwise, PFDs may
+        * not output clock after reset, MX6DL and MX6SL have added 396M pfd
+        * workaround in ROM code, as bus clock need it
+        */
+
+       mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
+               ANATOP_PFD_CLKGATE_MASK(1) |
+               ANATOP_PFD_CLKGATE_MASK(2) |
+               ANATOP_PFD_CLKGATE_MASK(3);
+       mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
+               ANATOP_PFD_CLKGATE_MASK(1) |
+               ANATOP_PFD_CLKGATE_MASK(3);
+
+       /*
+        * Don't reset PFD2 on DL/S
+        */
+       if (is_6q)
+               mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
+       writel(mask480, &anatop->pfd_480_set);
+       writel(mask528, &anatop->pfd_528_set);
+       writel(mask480, &anatop->pfd_480_clr);
+       writel(mask528, &anatop->pfd_528_clr);
 }
 
 #ifdef CONFIG_IMX_HDMI