ARM: zynq: Fix sparse warnings in slcr.c

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / zynq / slcr.c

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 788a8fd14f54f41a4c906620bdb1183b531d57c4..c326a4c5de3b5a7382a2eccc12c1e737d0470bea 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -1,33 +1,22 @@
 /*
  * Copyright (c) 2013 Xilinx Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/io.h>
 #include <malloc.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clk.h>
 
 #define SLCR_LOCK_MAGIC                0x767B
 #define SLCR_UNLOCK_MAGIC      0xDF0D
 
+#define SLCR_IDCODE_MASK       0x1F000
+#define SLCR_IDCODE_SHIFT      12
+
 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
 
 void zynq_slcr_lock(void)
@@ -61,3 +50,69 @@ void zynq_slcr_cpu_reset(void)
 
        writel(1, &slcr_base->pss_rst_ctrl);
 }
+
+/* Setup clk for network */
+void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
+{
+       int ret;
+
+       zynq_slcr_unlock();
+
+       if (gem_id > 1) {
+               printf("Non existing GEM id %d\n", gem_id);
+               goto out;
+       }
+
+       ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
+       if (ret)
+               goto out;
+
+       if (gem_id) {
+               /* Configure GEM_RCLK_CTRL */
+               writel(1, &slcr_base->gem1_rclk_ctrl);
+       } else {
+               /* Configure GEM_RCLK_CTRL */
+               writel(1, &slcr_base->gem0_rclk_ctrl);
+       }
+       udelay(100000);
+out:
+       zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_disable(void)
+{
+       zynq_slcr_unlock();
+
+       /* Disable AXI interface */
+       writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
+
+       /* Set Level Shifters DT618760 */
+       writel(0xA, &slcr_base->lvl_shftr_en);
+
+       zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_enable(void)
+{
+       zynq_slcr_unlock();
+
+       /* Set Level Shifters DT618760 */
+       writel(0xF, &slcr_base->lvl_shftr_en);
+
+       /* Disable AXI interface */
+       writel(0x0, &slcr_base->fpga_rst_ctrl);
+
+       zynq_slcr_lock();
+}
+
+u32 zynq_slcr_get_boot_mode(void)
+{
+       /* Get the bootmode register value */
+       return readl(&slcr_base->boot_mode);
+}
+
+u32 zynq_slcr_get_idcode(void)
+{
+       return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
+                                                       SLCR_IDCODE_SHIFT;
+}