ARM: tegra: Implement tegra_plle_enable()

[karo-tx-uboot.git] / arch / arm / cpu / tegra124-common / clock.c

diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/cpu/tegra124-common/clock.c
index 739436326ecaf78e1fc39a954ea06611d780ebad..fc8bd194ddc9d7bb29f8c1503939c58f4bf47066 100644 (file)
--- a/arch/arm/cpu/tegra124-common/clock.c
+++ b/arch/arm/cpu/tegra124-common/clock.c
@@ -824,3 +824,112 @@ void arch_timer_init(void)
        writel(val, &sysctr->cntcr);
        debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
 }
+
+#define PLLE_SS_CNTL 0x68
+#define  PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
+#define  PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
+#define  PLLE_SS_CNTL_SSCINVERT (1 << 15)
+#define  PLLE_SS_CNTL_SSCCENTER (1 << 14)
+#define  PLLE_SS_CNTL_SSCBYP (1 << 12)
+#define  PLLE_SS_CNTL_INTERP_RESET (1 << 11)
+#define  PLLE_SS_CNTL_BYPASS_SS (1 << 10)
+#define  PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
+
+#define PLLE_BASE 0x0e8
+#define  PLLE_BASE_ENABLE (1 << 30)
+#define  PLLE_BASE_LOCK_OVERRIDE (1 << 29)
+#define  PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
+#define  PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
+#define  PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
+
+#define PLLE_MISC 0x0ec
+#define  PLLE_MISC_IDDQ_SWCTL (1 << 14)
+#define  PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
+#define  PLLE_MISC_LOCK_ENABLE (1 << 9)
+#define  PLLE_MISC_PTS (1 << 8)
+#define  PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
+#define  PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
+
+#define PLLE_AUX 0x48c
+#define  PLLE_AUX_SEQ_ENABLE (1 << 24)
+#define  PLLE_AUX_ENABLE_SWCTL (1 << 4)
+
+int tegra_plle_enable(void)
+{
+       unsigned int m = 1, n = 200, cpcon = 13;
+       u32 value;
+
+       value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+       value &= ~PLLE_BASE_LOCK_OVERRIDE;
+       writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+       value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
+       value |= PLLE_AUX_ENABLE_SWCTL;
+       value &= ~PLLE_AUX_SEQ_ENABLE;
+       writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
+
+       udelay(1);
+
+       value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+       value |= PLLE_MISC_IDDQ_SWCTL;
+       value &= ~PLLE_MISC_IDDQ_OVERRIDE;
+       value |= PLLE_MISC_LOCK_ENABLE;
+       value |= PLLE_MISC_PTS;
+       value |= PLLE_MISC_VREG_BG_CTRL(3);
+       value |= PLLE_MISC_VREG_CTRL(2);
+       writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+       udelay(5);
+
+       value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+       value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
+                PLLE_SS_CNTL_BYPASS_SS;
+       writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+       value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+       value &= ~PLLE_BASE_PLDIV_CML(0xf);
+       value &= ~PLLE_BASE_NDIV(0xff);
+       value &= ~PLLE_BASE_MDIV(0xff);
+       value |= PLLE_BASE_PLDIV_CML(cpcon);
+       value |= PLLE_BASE_NDIV(n);
+       value |= PLLE_BASE_MDIV(m);
+       writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+       udelay(1);
+
+       value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+       value |= PLLE_BASE_ENABLE;
+       writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+       /* wait for lock */
+       udelay(300);
+
+       value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+       value &= ~PLLE_SS_CNTL_SSCINVERT;
+       value &= ~PLLE_SS_CNTL_SSCCENTER;
+
+       value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
+       value &= ~PLLE_SS_CNTL_SSCINC(0xff);
+       value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
+
+       value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
+       value |= PLLE_SS_CNTL_SSCINC(0x01);
+       value |= PLLE_SS_CNTL_SSCMAX(0x25);
+
+       writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+       value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+       value &= ~PLLE_SS_CNTL_SSCBYP;
+       value &= ~PLLE_SS_CNTL_BYPASS_SS;
+       writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+       udelay(1);
+
+       value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+       value &= ~PLLE_SS_CNTL_INTERP_RESET;
+       writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+       udelay(1);
+
+       return 0;
+}