S5P: Exynos: Add GPIO pin numbering and rename definitions

[karo-tx-uboot.git] / arch / arm / include / asm / arch-exynos / cpu.h

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index fdf73b507a60d7816d3e5744c66b86d827a6dda3..ba717146f51bf8589f68c5e8ed3ff23675c117b4 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -98,7 +98,7 @@
 #define EXYNOS5_I2C_SPACING            0x10000
 
 #define EXYNOS5_AUDIOSS_BASE           0x03810000
-#define EXYNOS5_GPIO_PART4_BASE                0x03860000
+#define EXYNOS5_GPIO_PART8_BASE                0x03860000
 #define EXYNOS5_PRO_ID                 0x10000000
 #define EXYNOS5_CLOCK_BASE             0x10010000
 #define EXYNOS5_POWER_BASE             0x10040000
@@ -108,9 +108,13 @@
 #define EXYNOS5_WATCHDOG_BASE          0x101D0000
 #define EXYNOS5_ACE_SFR_BASE           0x10830000
 #define EXYNOS5_DMC_PHY_BASE           0x10C00000
-#define EXYNOS5_GPIO_PART3_BASE                0x10D10000
+#define EXYNOS5_GPIO_PART5_BASE                0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE                0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE                0x10D100C0
 #define EXYNOS5_DMC_CTRL_BASE          0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE                0x11400000
+#define EXYNOS5_GPIO_PART2_BASE                0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE                0x11400C00
 #define EXYNOS5_MIPI_DSIM_BASE         0x11D00000
 #define EXYNOS5_USB_HOST_XHCI_BASE     0x12000000
 #define EXYNOS5_USB3PHY_BASE           0x12100000
@@ -125,7 +129,7 @@
 #define EXYNOS5_I2S_BASE               0x12D60000
 #define EXYNOS5_PWMTIMER_BASE          0x12DD0000
 #define EXYNOS5_SPI_ISP_BASE           0x131A0000
-#define EXYNOS5_GPIO_PART2_BASE                0x13400000
+#define EXYNOS5_GPIO_PART4_BASE                0x13400000
 #define EXYNOS5_FIMD_BASE              0x14400000
 #define EXYNOS5_DP_BASE                        0x145B0000
 
@@ -135,7 +139,7 @@
 
 /* EXYNOS5420 */
 #define EXYNOS5420_AUDIOSS_BASE                0x03810000
-#define EXYNOS5420_GPIO_PART5_BASE     0x03860000
+#define EXYNOS5420_GPIO_PART6_BASE     0x03860000
 #define EXYNOS5420_PRO_ID              0x10000000
 #define EXYNOS5420_CLOCK_BASE          0x10010000
 #define EXYNOS5420_POWER_BASE          0x10040000
@@ -158,8 +162,9 @@
 #define EXYNOS5420_PWMTIMER_BASE       0x12DD0000
 #define EXYNOS5420_SPI_ISP_BASE                0x131A0000
 #define EXYNOS5420_GPIO_PART2_BASE     0x13400000
-#define EXYNOS5420_GPIO_PART3_BASE     0x13410000
-#define EXYNOS5420_GPIO_PART4_BASE     0x14000000
+#define EXYNOS5420_GPIO_PART3_BASE     0x13400C00
+#define EXYNOS5420_GPIO_PART4_BASE     0x13410000
+#define EXYNOS5420_GPIO_PART5_BASE     0x14000000
 #define EXYNOS5420_GPIO_PART1_BASE     0x14010000
 #define EXYNOS5420_MIPI_DSIM_BASE      0x14500000
 #define EXYNOS5420_DP_BASE             0x145B0000