config: rename CONFIG_MX* to CONFIG_SOC_MX*

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx6 / crm_regs.h

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index d882d3b008c9c782699aca531fe42b3dacaa068d..261a7b38d0c3a4c52d381833a33f64f4b1775322 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -65,7 +65,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCR_WB_COUNT_MASK                      (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
 #define MXC_CCM_CCR_WB_COUNT_OFFSET                    (1 << 16)
 #define MXC_CCM_CCR_COSC_EN                            (1 << 12)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCR_OSCNT_MASK                         0x7F
 #else
 #define MXC_CCM_CCR_OSCNT_MASK                         0xFF
@@ -102,7 +102,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET          27
 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL                 (1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL                   (1 << 25)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK               (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET             19
 #endif
@@ -131,7 +131,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL             (1 << 20)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET                18
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK               (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET             16
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK             (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
@@ -139,7 +139,7 @@ struct mxc_ccm_reg {
 #endif
 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK             (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET           12
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL                   (1 << 11)
 #endif
 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL                 (1 << 10)
@@ -147,7 +147,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET      8
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET                4
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL                        (1 << 1)
 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL                        (1 << 0)
 #endif
@@ -155,7 +155,7 @@ struct mxc_ccm_reg {
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK              (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET            29
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK                 (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET               26
 #else
@@ -177,11 +177,11 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET             12
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK               (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET             10
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK              (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET            7
 #endif
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                        (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET              6
 #endif
@@ -189,7 +189,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                        (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
 
 /* Define the bits in register CSCMR2 */
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK                        (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET              21
 #endif
@@ -197,7 +197,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET             19
 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                 (1 << 11)
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                 (1 << 10)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                        (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET              8
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK               (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
@@ -208,7 +208,7 @@ struct mxc_ccm_reg {
 #endif
 
 /* Define the bits in register CSCDR1 */
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK               (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET             25
 #endif
@@ -220,18 +220,18 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET              16
 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK                        (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET              11
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET          8
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK            (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
 #endif
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
 #else
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
 #endif
 #endif
@@ -253,7 +253,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET            0
 
 /* Define the bits in register CS2CDR */
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK             (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET           21
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)               (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
@@ -284,7 +284,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET            0
 
 /* Define the bits in register CDCDR */
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK                 (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET               29
 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK              (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
@@ -304,7 +304,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET            7
 
 /* Define the bits in register CHSCCDR */
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK          (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET                15
 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK                 (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
@@ -363,7 +363,7 @@ struct mxc_ccm_reg {
 /* Define the bits in register CDHIPR */
 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY                   (1 << 16)
 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY             (1 << 5)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY              (1 << 4)
 #endif
 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY            (1 << 3)
@@ -374,14 +374,14 @@ struct mxc_ccm_reg {
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE                   (1 << 27)
 #define MXC_CCM_CLPCR_MASK_SCU_IDLE                    (1 << 26)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CLPCR_MASK_CORE3_WFI                   (1 << 25)
 #define MXC_CCM_CLPCR_MASK_CORE2_WFI                   (1 << 24)
 #define MXC_CCM_CLPCR_MASK_CORE1_WFI                   (1 << 23)
 #endif
 #define MXC_CCM_CLPCR_MASK_CORE0_WFI                   (1 << 22)
 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS              (1 << 21)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS              (1 << 19)
 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM                   (1 << 17)
 #endif
@@ -393,7 +393,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CLPCR_DIS_REF_OSC                      (1 << 7)
 #define MXC_CCM_CLPCR_SBYOS                            (1 << 6)
 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM               (1 << 5)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                        (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET              3
 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY          (1 << 2)
@@ -403,7 +403,7 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CISR */
 #define MXC_CCM_CISR_ARM_PODF_LOADED                   (1 << 26)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED              (1 << 23)
 #endif
 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED             (1 << 22)
@@ -416,7 +416,7 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CIMR */
 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED              (1 << 26)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED         (1 << 23)
 #endif
 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED                (1 << 22)
@@ -477,7 +477,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR0_DCIC1_MASK                       (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
 #define MXC_CCM_CCGR0_DCIC2_OFFSET                     26
 #define MXC_CCM_CCGR0_DCIC2_MASK                       (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET                  30
 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK                    (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
 #else
@@ -495,7 +495,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_ECSPI4S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET                   8
 #define MXC_CCM_CCGR1_ECSPI5S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET           10
 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK             (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
 #endif
@@ -505,7 +505,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_EPIT2S_MASK                      (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
 #define MXC_CCM_CCGR1_ESAIS_OFFSET                     16
 #define MXC_CCM_CCGR1_ESAIS_MASK                       (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR1_WAKEUP_OFFSET                    18
 #define MXC_CCM_CCGR1_WAKEUP_MASK                      (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
 #endif
@@ -513,27 +513,27 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_GPT_BUS_MASK                     (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET                        22
 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK                  (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR1_GPU2D_OFFSET                     24
 #define MXC_CCM_CCGR1_GPU2D_MASK                       (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
 #endif
 #define MXC_CCM_CCGR1_GPU3D_OFFSET                     26
 #define MXC_CCM_CCGR1_GPU3D_MASK                       (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET                   28
 #define MXC_CCM_CCGR1_OCRAM_S_MASK                     (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
 #define MXC_CCM_CCGR1_CANFD_OFFSET                     30
 #define MXC_CCM_CCGR1_CANFD_MASK                       (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
 #endif
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET           0
 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK             (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
 #else
 #define MXC_CCM_CCGR2_CSI_OFFSET                       2
 #define MXC_CCM_CCGR2_CSI_MASK                         (3 << MXC_CCM_CCGR2_CSI_OFFSET)
 #endif
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET           4
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK             (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
 #endif
@@ -555,7 +555,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPMUX3_MASK                      (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK   (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR2_LCD_OFFSET                       28
 #define MXC_CCM_CCGR2_LCD_MASK                         (3 << MXC_CCM_CCGR2_LCD_OFFSET)
 #define MXC_CCM_CCGR2_PXP_OFFSET                       30
@@ -567,7 +567,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK  (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
 #endif
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR3_M4_OFFSET                                        2
 #define MXC_CCM_CCGR3_M4_MASK                                  (3 << MXC_CCM_CCGR3_M4_OFFSET)
 #define MXC_CCM_CCGR3_ENET_OFFSET                              4
@@ -590,7 +590,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK                                (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET                           12
 #define MXC_CCM_CCGR3_LDB_DI0_MASK                             (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR3_QSPI1_OFFSET                             14
 #define MXC_CCM_CCGR3_QSPI1_MASK                               (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
 #else
@@ -603,7 +603,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_MLB_MASK                                 (3 << MXC_CCM_CCGR3_MLB_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET       20
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK         (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET       22
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK         (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
 #endif
@@ -613,14 +613,14 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK                        (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
 #define MXC_CCM_CCGR3_OCRAM_OFFSET                             28
 #define MXC_CCM_CCGR3_OCRAM_MASK                               (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET                      30
 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                                (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
 #endif
 
 #define MXC_CCM_CCGR4_PCIE_OFFSET                              0
 #define MXC_CCM_CCGR4_PCIE_MASK                                        (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET                                10
 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK                          (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
 #else
@@ -650,7 +650,7 @@ struct mxc_ccm_reg {
 
 #define MXC_CCM_CCGR5_ROM_OFFSET                       0
 #define MXC_CCM_CCGR5_ROM_MASK                         (3 << MXC_CCM_CCGR5_ROM_OFFSET)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR5_SATA_OFFSET                      4
 #define MXC_CCM_CCGR5_SATA_MASK                                (3 << MXC_CCM_CCGR5_SATA_OFFSET)
 #endif
@@ -670,7 +670,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR5_UART_MASK                                (3 << MXC_CCM_CCGR5_UART_OFFSET)
 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET               26
 #define MXC_CCM_CCGR5_UART_SERIAL_MASK                 (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR5_SAI1_OFFSET                      20
 #define MXC_CCM_CCGR5_SAI1_MASK                                (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
 #define MXC_CCM_CCGR5_SAI2_OFFSET                      30
@@ -1072,7 +1072,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR6_USDHC4_MASK                      (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET                  10
 #define MXC_CCM_CCGR6_EMI_SLOW_MASK                    (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define MXC_CCM_CCGR6_PWM8_OFFSET                      16
 #define MXC_CCM_CCGR6_PWM8_MASK                                (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
 #define MXC_CCM_CCGR6_VADC_OFFSET                      20