#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
/* Define the bits in register CBCMR */
+#if defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6DL)
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
+#else
+#define MXC_CCM_CBCMR_LCDIF_PODF_MASK (0x7 << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET)
+#define MXC_CCM_CBCMR_LCDIF_PODF_OFFSET 23
+#endif
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
- ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \
+ is_cpu_type(MXC_CPU_MX6ULL)) ? \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
- ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \
+ is_cpu_type(MXC_CPU_MX6ULL)) ? \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
- ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \
+ is_cpu_type(MXC_CPU_MX6ULL)) ? \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
/* All IPU2_DI1 are LCDIF1 on MX6SX */
+#if defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6DL)
#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
+#else
+#define MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CSCDR2_LCDIF_PRED_MASK (0x7 << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET)
+#define MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET 12
+#define MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET 9
+#endif
/* All IPU2_DI0 are LCDIF2 on MX6SX */
#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
#endif
-#ifndef CONFIG_SOC_MX6SX
-#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
-#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
-#else
+#if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL)
#define MXC_CCM_CCGR2_CSI_OFFSET 2
#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
+#else
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
#endif
-#ifndef CONFIG_SOC_MX6SX
+#if !defined(CONFIG_SOC_MX6SX) && !(defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL))
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
#endif
#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
-#ifdef CONFIG_SOC_MX6SX
+#if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
+ defined(CONFIG_SOC_MX6ULL)
#define MXC_CCM_CCGR2_LCD_OFFSET 28
#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
#define MXC_CCM_CCGR2_PXP_OFFSET 30
#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+/* IPU2_DI1 on i.MX6Q, i.MX6DL */
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+/* LCDIF on i.MX6UL */
+#define MXC_CCM_CCGR3_LCDIF_OFFSET 10
+#define MXC_CCM_CCGR3_LCDIF_MASK (3 << MXC_CCM_CCGR3_LCDIF_OFFSET)
+
#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)