#define MXC_CCM_CCR_RBC_EN (1 << 27)
#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
+/* CCR_WB does not exist on i.MX6SX/UL */
#define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
#define MXC_CCM_CCR_COSC_EN (1 << 12)
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
+/* Exists on i.MX6QP */
+#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
/* Define the bits in register CSR */
#define MXC_CCM_CSR_COSC_READY (1 << 5)
/* Define the bits in register CBCDR */
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
-#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
+#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
-#ifndef CONFIG_SOC_MX6SX
+/* MMDC_CH0 not exists on i.MX6SX */
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
-#endif
#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
+#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
#ifndef CONFIG_SOC_MX6SX
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
-#ifndef CONFIG_SOC_MX6SX
-#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
-#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
-#endif
+/* Exists on i.MX6QP */
+#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
/* Define the bits in register CSCMR1 */
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
-#ifdef CONFIG_SOC_MX6SX
+/* QSPI1 exist on i.MX6SX/UL */
#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
-#else
#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
-#endif
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
+/* CSCMR1_GPMI/BCH exist on i.MX6UL */
+#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
+#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
-#ifdef CONFIG_SOC_MX6SX
+/* QSPI1 exist on i.MX6SX/UL */
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
-#endif
-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
+/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
-#endif
-#define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0
-#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
+
+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
/* Define the bits in register CSCMR2 */
#ifdef CONFIG_SOC_MX6SX
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
-#ifdef CONFIG_SOC_MX6SX
+/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
+
#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
-#else
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
-#endif
/* Define the bits in register CSCDR1 */
#ifndef CONFIG_SOC_MX6SX
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
#endif
+/* CSCDR1_GPMI/BCH exist on i.MX6UL */
+#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)
+#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
+#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET)
+#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
+
#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
#endif
-#ifdef CONFIG_SOC_MX6SL
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
-#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
-#else
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
-#ifdef CONFIG_SOC_MX6SX
-#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
-#endif
-#endif
-#define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET 6
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
+/* UART_CLK_SEL exists on i.MX6SL/SX/QP */
+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
/* Define the bits in register CS1CDR */
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
/* Define the bits in register CS2CDR */
-#ifdef CONFIG_SOC_MX6SX
+/* QSPI2 on i.MX6SX */
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
-#else
+
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
-#endif
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
+
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
+
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
+
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
+/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
+
/* All IPU2_DI1 are LCDIF1 on MX6SX */
#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
-#ifndef CONFIG_SOC_MX6SX
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
-#endif
+/* CCGR1_ENET does not exist on i.MX6SX/UL */
+#define MXC_CCM_CCGR1_ENET_OFFSET 10
+#define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
#endif
-#ifdef CONFIG_SOC_MX6SX
+/* Exist on i.MX6SX */
#define MXC_CCM_CCGR3_M4_OFFSET 2
#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
#define MXC_CCM_CCGR3_ENET_OFFSET 4
#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
#define MXC_CCM_CCGR3_QSPI_OFFSET 14
#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
-#else
+
#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
-#endif
+
#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
-#ifdef CONFIG_SOC_MX6SX
+
+/* QSPI1 exists on i.MX6SX/UL */
#define MXC_CCM_CCGR3_QSPI1_OFFSET 14
#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
-#else
+
#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
-#endif
+
+/* A7_CLKDIV/WDOG1 on i.MX6UL */
+#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
+#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
+#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
+
#define MXC_CCM_CCGR3_MLB_OFFSET 18
#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+/* AXI on i.MX6UL */
+#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
+#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
-#ifndef CONFIG_SOC_MX6SX
+
+/* GPIO4 on i.MX6UL */
+#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
+#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
+
+#ifndef CONFIG_MX6SX
#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
#endif
#define MXC_CCM_CCGR4_PCIE_OFFSET 0
#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
-#ifdef CONFIG_SOC_MX6SX
+/* QSPI2 on i.MX6SX */
#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
-#else
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
-#endif
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
#endif
+/* PRG_CLK0 exists on i.MX6QP */
+#define MXC_CCM_CCGR6_PRG_CLK0_OFFSET 24
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
+
#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+/* GPMI/BCH on i.MX6UL */
+#define MXC_CCM_CCGR6_BCH_OFFSET 6
+#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
+#define MXC_CCM_CCGR6_GPMI_OFFSET 8
+#define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
+
#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
-#define BM_ANADIG_USB_PLL_480_CTRL_LOCK (1 << 31)
-#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS (1 << 16)
-#define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC 14
-#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
- (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) & \
- BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_USB_PLL_480_CTRL_ENABLE (1 << 13)
-#define BM_ANADIG_USB_PLL_480_CTRL_POWER (1 << 12)
-#define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP (1 << 9)
-#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF (1 << 7)
-#define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
-#define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0 2
-#define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0)
-#define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v) \
- (((v) << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) & \
- BM_ANADIG_USB_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT 0
-#define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
-#define BF_ANADIG_USB_PLL_480_CTRL_DIV_SELECT(v) \
- (((v) << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) & \
- BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
+#define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
+#define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
+#define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
+#define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
+#define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_ARM_DIV_SELECT 0
+#define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
+#define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
+ BM_ANADIG_PLL_ARM_DIV_SELECT)
+
+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31)
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16)
+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) & \
+ BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13)
+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9)
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7)
+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
+ (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \
+ BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \
+ BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
#define BM_ANADIG_PLL_528_LOCK (1 << 31)
#define BM_ANADIG_PLL_528_PLL_SEL (1 << 19)
#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
-#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
-#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
- (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & \
- BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT)
+#define BF_ANADIG_PLL_AUDIO_POST_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT) & \
+ BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT)
#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
(((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
BM_ANADIG_PLL_VIDEO_DENOM_B)
+#define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
+#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
+#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
+#define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
+#define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
+#define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_MLB_PHASE_SEL 12
+#define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
+#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
+ (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
+ BM_ANADIG_PLL_MLB_PHASE_SEL)
+#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
+
#define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE (1 << 21)
#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
(((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
BM_ANADIG_PFD_528_PFD0_FRAC)
+#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
+#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
+ BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25)
+#define BP_ANADIG_ANA_MISC0_ANAMUX 21
+#define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
+#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
+ BM_ANADIG_ANA_MISC0_ANAMUX)
+#define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20)
+#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
+#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
+ BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
+#define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
+#define BP_ANADIG_ANA_MISC0_OSC_I 14
+#define BM_ANADIG_ANA_MISC0_OSC_I (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
+#define BF_ANADIG_ANA_MISC0_OSC_I(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
+ BM_ANADIG_ANA_MISC0_OSC_I)
+#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13)
+#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
+#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
+#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
+#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
+ BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
+#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
+#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \
+ BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
+#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
+#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
+#define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
+
+#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
+#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30)
+#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO (1 << 29)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
+#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
+#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
+#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
+ (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \
+ BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
+#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
+#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
+#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
+ (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \
+ BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
+
+#define BP_ANADIG_ANA_MISC2_CONTROL3 30
+#define BM_ANADIG_ANA_MISC2_CONTROL3 (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3)
+#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \
+ BM_ANADIG_ANA_MISC2_CONTROL3)
+#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
+#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME)
+#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \
+ BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
+#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
+#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME)
+#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \
+ BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
+#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
+#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME)
+#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \
+ BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
+#define BM_ANADIG_ANA_MISC2_CONTROL2 (1 << 23)
+#define BM_ANADIG_ANA_MISC2_REG2_OK (1 << 22)
+#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
+#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19)
+#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
+#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
+#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \
+ BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
+#define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
+#define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
+#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13)
+#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
+#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
+#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET
+#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \
+ BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
+#define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7)
+#define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6)
+#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5)
+#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3)
+#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
+#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
+#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \
+ BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
+
+#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
+#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
+#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
+ (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \
+ BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
+#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
+#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
+#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
+ (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \
+ BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
+#define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
+#define BP_ANADIG_TEMPSENSE0_VBGADJ 3
+#define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
+#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \
+ (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \
+ BM_ANADIG_TEMPSENSE0_VBGADJ)
+#define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
+#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
+#define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
+
+#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
+#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
+#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
+ (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \
+ BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
+
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
projects / karo-tx-uboot.git / blobdiff