mx6: Revert "mx6: soc: Disable VDDPU regulator"

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 0e4d8fa73d69c5606921ec7d86b422038dfc0cd6..f2ad6e9ad32fffda215e8beb8901d8ecff69a727 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -1,19 +1,7 @@
 /*
  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
@@ -229,7 +217,6 @@
 
 #define CHIP_REV_1_0                 0x10
 #define IRAM_SIZE                    0x00040000
-#define IMX_IIM_BASE                 OCOTP_BASE_ADDR
 #define FEC_QUIRK_ENET_MAC
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
@@ -258,11 +245,9 @@ struct src {
        u32     gpr10;
 };
 
-/* OCOTP Registers */
-struct ocotp_regs {
-       u32     reserved[0x198];
-       u32     gp1;    /* 0x660 */
-};
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET                21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK          (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
 
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET             29
@@ -371,7 +356,7 @@ struct iomuxc {
 
 #define IOMUXC_GPR2_MODE_DISABLED      0
 #define IOMUXC_GPR2_MODE_ENABLED_DI0   1
-#define IOMUXC_GPR2_MODE_ENABLED_DI1   2
+#define IOMUXC_GPR2_MODE_ENABLED_DI1   3
 
 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET               2
 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK                 (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
@@ -438,7 +423,7 @@ struct cspi_regs {
        ECSPI5_BASE_ADDR
 #endif
 
-struct iim_regs {
+struct ocotp_regs {
        u32     ctrl;
        u32     ctrl_set;
        u32     ctrl_clr;
@@ -449,9 +434,9 @@ struct iim_regs {
        u32     rsvd1[3];
        u32     read_ctrl;
        u32     rsvd2[3];
-       u32     fuse_data;
+       u32     read_fuse_data;
        u32     rsvd3[3];
-       u32     sticky;
+       u32     sw_sticky;
        u32     rsvd4[3];
        u32     scs;
        u32     scs_set;
@@ -466,7 +451,22 @@ struct iim_regs {
 
        struct fuse_bank {
                u32     fuse_regs[0x20];
-       } bank[15];
+       } bank[16];
+};
+
+struct fuse_bank0_regs {
+       u32     lock;
+       u32     rsvd0[3];
+       u32     uid_low;
+       u32     rsvd1[3];
+       u32     uid_high;
+       u32     rsvd2[3];
+       u32     rsvd3[4];
+       u32     rsvd4[4];
+       u32     rsvd5[4];
+       u32     cfg5;
+       u32     rsvd6[3];
+       u32     rsvd7[4];
 };
 
 struct fuse_bank4_regs {
@@ -477,7 +477,11 @@ struct fuse_bank4_regs {
        u32     mac_addr_low;
        u32     rsvd2[3];
        u32     mac_addr_high;
-       u32     rsvd3[0x13];
+       u32     rsvd3[0xb];
+       u32     gp1;
+       u32     rsvd4[3];
+       u32     gp2;
+       u32     rsvd5[3];
 };
 
 struct aipstz_regs {
@@ -635,29 +639,12 @@ struct anatop_regs {
        u32     digprog_sololite;       /* 0x280 */
 };
 
-#define ANATOP_PFD_480_PFD0_FRAC_SHIFT         0
-#define ANATOP_PFD_480_PFD0_FRAC_MASK          (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD0_STABLE_SHIFT       6
-#define ANATOP_PFD_480_PFD0_STABLE_MASK                (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT      7
-#define ANATOP_PFD_480_PFD0_CLKGATE_MASK       (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD1_FRAC_SHIFT         8
-#define ANATOP_PFD_480_PFD1_FRAC_MASK          (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD1_STABLE_SHIFT       14
-#define ANATOP_PFD_480_PFD1_STABLE_MASK                (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT      15
-#define ANATOP_PFD_480_PFD1_CLKGATE_MASK       (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD2_FRAC_SHIFT         16
-#define ANATOP_PFD_480_PFD2_FRAC_MASK          (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD2_STABLE_SHIFT       22
-#define ANATOP_PFD_480_PFD2_STABLE_MASK        (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT      23
-#define ANATOP_PFD_480_PFD2_CLKGATE_MASK       (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD3_FRAC_SHIFT         24
-#define ANATOP_PFD_480_PFD3_FRAC_MASK          (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD3_STABLE_SHIFT       30
-#define ANATOP_PFD_480_PFD3_STABLE_MASK                (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT      31
+#define ANATOP_PFD_FRAC_SHIFT(n)       ((n)*8)
+#define ANATOP_PFD_FRAC_MASK(n)        (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
+#define ANATOP_PFD_STABLE_SHIFT(n)     (6+((n)*8))
+#define ANATOP_PFD_STABLE_MASK(n)      (1<<ANATOP_PFD_STABLE_SHIFT(n))
+#define ANATOP_PFD_CLKGATE_SHIFT(n)    (7+((n)*8))
+#define ANATOP_PFD_CLKGATE_MASK(n)     (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
 
 struct iomuxc_base_regs {
        u32     gpr[14];        /* 0x000 */