mx6sxsabresd: Add Ethernet support

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx6 / iomux.h

diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index fe4675e0b7fb6143715acdee78a9cb05e5183ebc..f54db6944dddd9b62ad0b6bcfd791d8dda3db53c 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -15,6 +15,33 @@
 #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13)
 #define IOMUXC_GPR1_OTG_ID_GPIO1       (1<<13)
 #define IOMUXC_GPR1_OTG_ID_MASK                (1<<13)
+#define IOMUXC_GPR1_REF_SSP_EN                 (1 << 16)
+#define IOMUXC_GPR1_TEST_POWERDOWN             (1 << 18)
+
+/*
+ * IOMUXC_GPR8 bit fields
+ */
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK            (0x3f << 0)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET          0
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK      (0x3f << 6)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET    6
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK                (0x3f << 12)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET      12
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK             (0x7f << 18)
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET           18
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK              (0x7f << 25)
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET            25
+
+/*
+ * IOMUXC_GPR12 bit fields
+ */
+#define IOMUXC_GPR12_LOS_LEVEL_9               (0x9 << 4)
+#define IOMUXC_GPR12_LOS_LEVEL_MASK            (0x1f << 4)
+#define IOMUXC_GPR12_APPS_LTSSM_ENABLE         (1 << 10)
+#define IOMUXC_GPR12_DEVICE_TYPE_EP            (0x0 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC            (0x4 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_MASK          (0xf << 12)
+
 /*
  * IOMUXC_GPR13 bit fields
  */
@@ -38,6 +65,16 @@
 #define IOMUX_GPR1_FEC_MASK    (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
                                | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
 
+#define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17)
+#define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13)
+#define IOMUX_GPR1_FEC1_MASK   (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \
+                               | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK)
+
+#define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18)
+#define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+#define IOMUX_GPR1_FEC2_MASK   (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \
+                               | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK)
+
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB     (0<<24)
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB     (1<<24)
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB     (2<<24)