arm: mx6: add support for i.MX6ULL

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx6 / mx6-ddr.h

diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index d544d2e7086009fc0d083816b6233610af556221..8004c67ae0fd9a172758ce1830c62a186eee4f24 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -7,15 +7,17 @@
 #define __ASM_ARCH_MX6_DDR_H__
 
 #ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
 #include "mx6q-ddr.h"
-#else
-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 #include "mx6dl-ddr.h"
+#elif defined(CONFIG_SOC_MX6SX)
+#include "mx6sx-ddr.h"
+#elif defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)
+#include "mx6ul-ddr.h"
 #else
 #error "Please select cpu"
-#endif /* CONFIG_MX6DL or CONFIG_MX6S */
-#endif /* CONFIG_MX6Q */
+#endif
 #else
 
 /* MMDC P0/P1 Registers */
@@ -58,6 +60,87 @@ struct mmdc_p_regs {
        u32 mpmur0;
 };
 
+#define MX6UL_IOM_DDR_BASE     0x020e0200
+struct mx6ul_iomux_ddr_regs {
+       u32 res1[17];
+       u32 dram_dqm0;
+       u32 dram_dqm1;
+       u32 dram_ras;
+       u32 dram_cas;
+       u32 dram_cs0;
+       u32 dram_cs1;
+       u32 dram_sdwe_b;
+       u32 dram_odt0;
+       u32 dram_odt1;
+       u32 dram_sdba0;
+       u32 dram_sdba1;
+       u32 dram_sdba2;
+       u32 dram_sdcke0;
+       u32 dram_sdcke1;
+       u32 dram_sdclk_0;
+       u32 dram_sdqs0;
+       u32 dram_sdqs1;
+       u32 dram_reset;
+};
+
+#define MX6UL_IOM_GRP_BASE     0x020e0400
+struct mx6ul_iomux_grp_regs {
+       u32 res1[36];
+       u32 grp_addds;
+       u32 grp_ddrmode_ctl;
+       u32 grp_b0ds;
+       u32 grp_ddrpk;
+       u32 grp_ctlds;
+       u32 grp_b1ds;
+       u32 grp_ddrhys;
+       u32 grp_ddrpke;
+       u32 grp_ddrmode;
+       u32 grp_ddr_type;
+};
+
+#define MX6SX_IOM_DDR_BASE     0x020e0200
+struct mx6sx_iomux_ddr_regs {
+       u32 res1[59];
+       u32 dram_dqm0;
+       u32 dram_dqm1;
+       u32 dram_dqm2;
+       u32 dram_dqm3;
+       u32 dram_ras;
+       u32 dram_cas;
+       u32 res2[2];
+       u32 dram_sdwe_b;
+       u32 dram_odt0;
+       u32 dram_odt1;
+       u32 dram_sdba0;
+       u32 dram_sdba1;
+       u32 dram_sdba2;
+       u32 dram_sdcke0;
+       u32 dram_sdcke1;
+       u32 dram_sdclk_0;
+       u32 dram_sdqs0;
+       u32 dram_sdqs1;
+       u32 dram_sdqs2;
+       u32 dram_sdqs3;
+       u32 dram_reset;
+};
+
+#define MX6SX_IOM_GRP_BASE     0x020e0500
+struct mx6sx_iomux_grp_regs {
+       u32 res1[61];
+       u32 grp_addds;
+       u32 grp_ddrmode_ctl;
+       u32 grp_ddrpke;
+       u32 grp_ddrpk;
+       u32 grp_ddrhys;
+       u32 grp_ddrmode;
+       u32 grp_b0ds;
+       u32 grp_b1ds;
+       u32 grp_ctlds;
+       u32 grp_ddr_type;
+       u32 grp_b2ds;
+       u32 grp_b3ds;
+};
+
 /*
  * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
  */
@@ -203,6 +286,7 @@ struct mx6_ddr_sysinfo {
        u8 mif3_mode;   /* Command prediction working mode */
        u8 rst_to_cke;  /* Time from SDE enable to CKE rise */
        u8 sde_to_rst;  /* Time from SDE enable until DDR reset# is high */
+       u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
 };
 
 /*
@@ -239,6 +323,12 @@ void mx6dq_dram_iocfg(unsigned width,
 void mx6sdl_dram_iocfg(unsigned width,
                       const struct mx6sdl_iomux_ddr_regs *,
                       const struct mx6sdl_iomux_grp_regs *);
+void mx6sx_dram_iocfg(unsigned width,
+                     const struct mx6sx_iomux_ddr_regs *,
+                     const struct mx6sx_iomux_grp_regs *);
+void mx6ul_dram_iocfg(unsigned width,
+                     const struct mx6ul_iomux_ddr_regs *,
+                     const struct mx6ul_iomux_grp_regs *);
 
 /* configure mx6 mmdc registers */
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,