* Texas Instruments, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _MEM_H_
#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */
-#define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \
- ACTIM_CTRLA_TRFC(a) | \
- ACTIM_CTRLA_TRC(b) | \
- ACTIM_CTRLA_TRAS(b) | \
- ACTIM_CTRLA_TRP(d) | \
- ACTIM_CTRLA_TRCD(e) | \
- ACTIM_CTRLA_TRRD(f) | \
- ACTIM_CTRLA_TDPL(g) | \
- ACTIM_CTRLA_TDAL(h)
+#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \
+ ACTIM_CTRLA_TRFC(trfc) | \
+ ACTIM_CTRLA_TRC(trc) | \
+ ACTIM_CTRLA_TRAS(tras) | \
+ ACTIM_CTRLA_TRP(trp) | \
+ ACTIM_CTRLA_TRCD(trcd) | \
+ ACTIM_CTRLA_TRRD(trrd) | \
+ ACTIM_CTRLA_TDPL(tdpl) | \
+ ACTIM_CTRLA_TDAL(tdal)
/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */
#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */
#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */
-#define ACTIM_CTRLB(a,b,c,d) \
- ACTIM_CTRLB_TWTR(a) | \
- ACTIM_CTRLB_TCKE(b) | \
- ACTIM_CTRLB_TXP(b) | \
- ACTIM_CTRLB_TXSR(d)
+#define ACTIM_CTRLB(twtr, tcke, txp, txsr) \
+ ACTIM_CTRLB_TWTR(twtr) | \
+ ACTIM_CTRLB_TCKE(tcke) | \
+ ACTIM_CTRLB_TXP(txp) | \
+ ACTIM_CTRLB_TXSR(txsr)
/*
* Values used in the MCFG register. Only values we use today
#define V_MCFG_RAMTYPE_DDR (0x1)
#define V_MCFG_DEEPPD_EN (0x1 << 3)
#define V_MCFG_B32NOT16_32 (0x1 << 4)
-#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
-#define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */
+#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
+#define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8) /* 8:17 */
#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
-#define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */
-#define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */
+#define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */
+#define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10)
+#define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */
/* Macro to construct MCFG */
-#define MCFG(a, b) \
- V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \
- V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \
- V_MCFG_BANKALLOCATION_RBC | \
- V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
+#define MCFG(ramsize, raswidth) \
+ V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \
+ V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \
+ V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \
+ V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
+
+/* Hynix part of Overo (165MHz optimized) 6.06ns */
+#define HYNIX_TDAL_165 6
+#define HYNIX_TDPL_165 3
+#define HYNIX_TRRD_165 2
+#define HYNIX_TRCD_165 3
+#define HYNIX_TRP_165 3
+#define HYNIX_TRAS_165 7
+#define HYNIX_TRC_165 10
+#define HYNIX_TRFC_165 21
+#define HYNIX_V_ACTIMA_165 \
+ ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \
+ HYNIX_TRAS_165, HYNIX_TRP_165, \
+ HYNIX_TRCD_165, HYNIX_TRRD_165, \
+ HYNIX_TDPL_165, HYNIX_TDAL_165)
+
+#define HYNIX_TWTR_165 1
+#define HYNIX_TCKE_165 1
+#define HYNIX_TXP_165 2
+#define HYNIX_XSR_165 24
+#define HYNIX_V_ACTIMB_165 \
+ ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \
+ HYNIX_TXP_165, HYNIX_XSR_165)
+
+#define HYNIX_RASWIDTH_165 13
+#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165)
+
+/* Hynix part of AM/DM37xEVM (200MHz optimized) */
+#define HYNIX_TDAL_200 6
+#define HYNIX_TDPL_200 3
+#define HYNIX_TRRD_200 2
+#define HYNIX_TRCD_200 4
+#define HYNIX_TRP_200 3
+#define HYNIX_TRAS_200 8
+#define HYNIX_TRC_200 11
+#define HYNIX_TRFC_200 18
+#define HYNIX_V_ACTIMA_200 \
+ ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
+ HYNIX_TRAS_200, HYNIX_TRP_200, \
+ HYNIX_TRCD_200, HYNIX_TRRD_200, \
+ HYNIX_TDPL_200, HYNIX_TDAL_200)
+
+#define HYNIX_TWTR_200 2
+#define HYNIX_TCKE_200 1
+#define HYNIX_TXP_200 1
+#define HYNIX_XSR_200 28
+#define HYNIX_V_ACTIMB_200 \
+ ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
+ HYNIX_TXP_200, HYNIX_XSR_200)
+
+#define HYNIX_RASWIDTH_200 14
+#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
MICRON_TXP_165, MICRON_XSR_165)
-#define MICRON_RASWIDTH_165 0x2
+#define MICRON_RASWIDTH_165 13
#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165)
#define MICRON_BL_165 0x2
(MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
(MICRON_BL_165))
+/* Micron part (200MHz optimized) 5 ns */
+#define MICRON_TDAL_200 6
+#define MICRON_TDPL_200 3
+#define MICRON_TRRD_200 2
+#define MICRON_TRCD_200 3
+#define MICRON_TRP_200 3
+#define MICRON_TRAS_200 8
+#define MICRON_TRC_200 11
+#define MICRON_TRFC_200 15
+#define MICRON_V_ACTIMA_200 \
+ ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \
+ MICRON_TRAS_200, MICRON_TRP_200, \
+ MICRON_TRCD_200, MICRON_TRRD_200, \
+ MICRON_TDPL_200, MICRON_TDAL_200)
+
+#define MICRON_TWTR_200 2
+#define MICRON_TCKE_200 4
+#define MICRON_TXP_200 2
+#define MICRON_XSR_200 23
+#define MICRON_V_ACTIMB_200 \
+ ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \
+ MICRON_TXP_200, MICRON_XSR_200)
+
+#define MICRON_RASWIDTH_200 14
+#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
+
/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
/* 15/6 + 18/6 = 5.5 -> 6 */
ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
NUMONYX_TXP_165, NUMONYX_XSR_165)
-#ifdef CONFIG_OMAP3_INFINEON_DDR
-#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
-#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
-#endif
-
-#ifdef CONFIG_OMAP3_MICRON_DDR
-#define V_ACTIMA_165 MICRON_V_ACTIMA_165
-#define V_ACTIMB_165 MICRON_V_ACTIMB_165
-#define V_MCFG MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE)
-#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
-#define V_MR MICRON_V_MR_165
-#endif
-
-#ifdef CONFIG_OMAP3_NUMONYX_DDR
-#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
-#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
-#endif
-
-#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
-#error "Please choose the right DDR type in config header"
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL))
-#error "Please choose the right DDR type in config header"
-#endif
+#define NUMONYX_RASWIDTH_165 15
+#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
+
+/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
+#define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */
+ /* 15/5 + 15/5 = 3 + 3 -> 6 */
+#define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */
+#define NUMONYX_TRRD_200 2 /* 10/5 = 2 */
+#define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */
+#define NUMONYX_TRP_200 3 /* 15/5 = 3 */
+#define NUMONYX_TRAS_200 8 /* 40/5 = 8 */
+#define NUMONYX_TRC_200 11 /* 55/5 = 11 */
+#define NUMONYX_TRFC_200 28 /* 140/5 = 28 */
+
+#define NUMONYX_V_ACTIMA_200 \
+ ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \
+ NUMONYX_TRAS_200, NUMONYX_TRP_200, \
+ NUMONYX_TRCD_200, NUMONYX_TRRD_200, \
+ NUMONYX_TDPL_200, NUMONYX_TDAL_200)
+
+#define NUMONYX_TWTR_200 2
+#define NUMONYX_TCKE_200 2
+#define NUMONYX_TXP_200 3
+#define NUMONYX_XSR_200 40
+
+#define NUMONYX_V_ACTIMB_200 \
+ ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \
+ NUMONYX_TXP_200, NUMONYX_XSR_200)
+
+#define NUMONYX_RASWIDTH_200 15
+#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200)
/*
* GPMC settings -
#define NET_GPMC_CONFIG6 0x00000FCF
#define NET_GPMC_CONFIG7 0x00000f6c
+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1 0x00001000
+#define NET_LAN9221_GPMC_CONFIG2 0x00060700
+#define NET_LAN9221_GPMC_CONFIG3 0x00020201
+#define NET_LAN9221_GPMC_CONFIG4 0x06000700
+#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
+#define NET_LAN9221_GPMC_CONFIG6 0x87030000
+#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
+
+
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */
projects / karo-tx-uboot.git / blobdiff