ARM: omap4: add platform specific info for GPMC and ELM controllers

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap4 / omap.h

diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 44353a43f2591b956dce5a1a9fd13e9de050aef1..d43dc265cd68f952897d07b39fbf691fbe281fdf 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -9,23 +9,7 @@
  *     Richard Woodruff <r-woodruff2@ti.com>
  *     Syed Mohammed Khasim <x0khasim@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _OMAP4_H_
@@ -47,16 +31,12 @@
 #define DRAM_ADDR_SPACE_START  OMAP44XX_DRAM_ADDR_SPACE_START
 #define DRAM_ADDR_SPACE_END    OMAP44XX_DRAM_ADDR_SPACE_END
 
-/* CONTROL */
-#define CTRL_BASE              (OMAP44XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE   (OMAP44XX_L4_CORE_BASE + 0x100000)
-#define CONTROL_PADCONF_WKUP   (OMAP44XX_L4_CORE_BASE + 0x31E000)
-
-/* LPDDR2 IO regs */
-#define LPDDR2_IO_REGS_BASE    0x4A100638
-
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE                0x4A002204
+#define STD_FUSE_DIE_ID_0      0x4A002200
+#define STD_FUSE_DIE_ID_1      0x4A002208
+#define STD_FUSE_DIE_ID_2      0x4A00220c
+#define STD_FUSE_DIE_ID_3      0x4A002210
 
 #define OMAP4_CONTROL_ID_CODE_ES1_0    0x0B85202F
 #define OMAP4_CONTROL_ID_CODE_ES2_0    0x1B85202F
@@ -65,6 +45,7 @@
 #define OMAP4_CONTROL_ID_CODE_ES2_3    0x6B95C02F
 #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
 #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
+#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F
 
 /* UART */
 #define UART1_BASE             (OMAP44XX_L4_PER_BASE + 0x6a000)
@@ -79,15 +60,6 @@
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE              (OMAP44XX_L4_WKUP_BASE + 0x14000)
 
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE     (OMAP44XX_L4_WKUP_BASE + 0x4000)
-
-/* GPMC */
-#define OMAP44XX_GPMC_BASE     0x50000000
-
-/* SYSTEM CONTROL MODULE */
-#define SYSCTRL_GENERAL_CORE_BASE      0x4A002000
-
 /*
  * Hardware Register Details
  */
@@ -141,7 +113,15 @@ struct s32ktimer {
  */
 #define NON_SECURE_SRAM_START  0x40304000
 #define NON_SECURE_SRAM_END    0x4030E000      /* Not inclusive */
-#define SRAM_SCRATCH_SPACE_ADDR        NON_SECURE_SRAM_START
+#define SRAM_SCRATCH_SPACE_ADDR        0x4030C000
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE     0x4030D000
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME         50
+#define OMAP_ABB_CLOCK_CYCLES          16
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK       (0x1 << 7)
+
 #endif