armv7:TI: Add <asm/ti-common/sys_proto.h> and migrate omap_hw_init_context

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap5 / omap.h

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index e9a51d340381fbe94bd608e10776db3a2272c455..b9600cf42dbc5a03c384b5271e77b301cb3f2618 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -23,11 +23,6 @@
 #define OMAP54XX_L4_WKUP_BASE  0x4Ae00000
 #define OMAP54XX_L4_PER_BASE   0x48000000
 
-#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
-#define OMAP54XX_DRAM_ADDR_SPACE_END   0xFFFFFFFF
-#define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
-#define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
-
 /* CONTROL ID CODE */
 #define CONTROL_CORE_ID_CODE   0x4A002204
 #define CONTROL_WKUP_ID_CODE   0x4AE0C204
@@ -44,11 +39,14 @@
 #define OMAP5432_CONTROL_ID_CODE_ES1_0         0x0B99802F
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 #define DRA752_CONTROL_ID_CODE_ES1_0           0x0B99002F
+#define DRA752_CONTROL_ID_CODE_ES1_1           0x1B99002F
+#define DRA722_CONTROL_ID_CODE_ES1_0           0x0B9BC02F
 
 /* UART */
 #define UART1_BASE             (OMAP54XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE             (OMAP54XX_L4_PER_BASE + 0x6c000)
 #define UART3_BASE             (OMAP54XX_L4_PER_BASE + 0x20000)
+#define UART4_BASE             (OMAP54XX_L4_PER_BASE + 0x6e000)
 
 /* General Purpose Timers */
 #define GPT1_BASE              (OMAP54XX_L4_WKUP_BASE + 0x18000)
@@ -58,8 +56,11 @@
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE              (OMAP54XX_L4_WKUP_BASE + 0x14000)
 
-/* GPMC */
-#define OMAP54XX_GPMC_BASE     0x50000000
+/* QSPI */
+#define QSPI_BASE              0x4B300000
+
+/* SATA */
+#define DWC_AHSATA_BASE                0x4A140000
 
 /*
  * Hardware Register Details
@@ -142,9 +143,9 @@ struct s32ktimer {
 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE                         0x0
 
 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
-#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
-#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
 
 #define EFUSE_1 0x45145100
@@ -198,6 +199,8 @@ struct s32ktimer {
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK               (0x1F << 24)
 #define OMAP5_ABB_FUSE_ENABLE_MASK             (0x1 << 29)
+#define DRA7_ABB_FUSE_VSET_MASK                        (0x1F << 20)
+#define DRA7_ABB_FUSE_ENABLE_MASK              (0x1 << 25)
 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK      (0x1 << 10)
 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK      (0x1f << 0)
 
@@ -236,6 +239,7 @@ struct ctrl_ioregs {
        u32 ctrl_ddrio_1;
        u32 ctrl_ddrio_2;
        u32 ctrl_emif_sdram_config_ext;
+       u32 ctrl_emif_sdram_config_ext_final;
        u32 ctrl_ddr_ctrl_ext_0;
 };