Merge 'u-boot-microblaze/zynq' into (u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / include / asm / arch-zynq / hardware.h

diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index 8eb4e1a7a96adf6fd9ab8c24a0ac1ee0c5531867..cd69677729cbf81ad237e1ac64b8477fde37e1f3 100644 (file)
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -1,23 +1,7 @@
 /*
  * Copyright (c) 2013 Xilinx Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _ASM_ARCH_HARDWARE_H
@@ -31,6 +15,11 @@
 #define ZYNQ_GEM_BASEADDR1             0xE000C000
 #define ZYNQ_SDHCI_BASEADDR0           0xE0100000
 #define ZYNQ_SDHCI_BASEADDR1           0xE0101000
+#define ZYNQ_I2C_BASEADDR0             0xE0004000
+#define ZYNQ_I2C_BASEADDR1             0xE0005000
+#define ZYNQ_SPI_BASEADDR0             0xE0006000
+#define ZYNQ_SPI_BASEADDR1             0xE0007000
+#define ZYNQ_DDRC_BASEADDR             0xF8006000
 
 /* Reflect slcr offsets */
 struct slcr_regs {
@@ -51,11 +40,17 @@ struct slcr_regs {
        u32 boot_mode; /* 0x25c */
        u32 reserved4[116];
        u32 trust_zone; /* 0x430 */ /* FIXME */
-       u32 reserved5[115];
+       u32 reserved5_1[63];
+       u32 pss_idcode; /* 0x530 */
+       u32 reserved5_2[51];
        u32 ddr_urgent; /* 0x600 */
        u32 reserved6[6];
        u32 ddr_urgent_sel; /* 0x61c */
-       u32 reserved7[188];
+       u32 reserved7[56];
+       u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+       u32 reserved8[74];
+       u32 lvl_shftr_en; /* 0x900 */
+       u32 reserved9[3];
        u32 ocm_cfg; /* 0x910 */
 };
 
@@ -92,4 +87,11 @@ struct scu_regs {
 
 #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
 
+struct ddrc_regs {
+       u32 ddrc_ctrl; /* 0x0 */
+       u32 reserved[60];
+       u32 ecc_scrub; /* 0xF4 */
+};
+#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
+
 #endif /* _ASM_ARCH_HARDWARE_H */