*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __MACH_IOMUX_V3_H__
-#define __MACH_IOMUX_V3_H__
+#ifndef __ASM_ARCH_IOMUX_V3_H__
+#define __ASM_ARCH_IOMUX_V3_H__
+
+#include <common.h>
/*
* build IOMUX_PAD structure
*
* IOMUX/PAD Bit field definitions
*
- * MUX_CTRL_OFS: 0..11 (12)
- * PAD_CTRL_OFS: 12..23 (12)
- * SEL_INPUT_OFS: 24..35 (12)
- * MUX_MODE + SION: 36..40 (5)
- * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
- * SEL_INP: 59..62 (4)
- * reserved: 63 (1)
+ * MUX_CTRL_OFS: 0..11 (12)
+ * PAD_CTRL_OFS: 12..23 (12)
+ * SEL_INPUT_OFS: 24..35 (12)
+ * MUX_MODE + SION: 36..40 (5)
+ * PAD_CTRL + PAD_CTRL_VALID: 41..58 (18)
+ * SEL_INP: 59..62 (4)
+ * reserved: 63 (1)
*/
typedef u64 iomux_v3_cfg_t;
#define MUX_MODE_SHIFT 36
#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
#define MUX_PAD_CTRL_SHIFT 41
-#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
+#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
#define MUX_SEL_INPUT_SHIFT 59
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
-#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
+ MUX_MODE_SHIFT)
+#define __MUX_PAD_CTRL(x) ((x) | __PAD_CTRL_VALID)
+#define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)__MUX_PAD_CTRL(x) << \
+ MUX_PAD_CTRL_SHIFT))
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
sel_input, pad_ctrl) \
((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
-#define NO_PAD_CTRL (1 << 17)
+#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
+ MUX_PAD_CTRL(pad))
+
+#define __NA_ 0x000
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+
+#define NO_PAD_CTRL 0
+#define __PAD_CTRL_VALID (1 << 17)
+#define PAD_CTRL_VALID ((iomux_v3_cfg_t)__PAD_CTRL_VALID << MUX_PAD_CTRL_SHIFT)
+
+#ifdef CONFIG_ARCH_MX6
+
+#define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 16)
+
+#define PAD_CTL_PUS_100K_DOWN __MUX_PAD_CTRL(0 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 13 | PAD_CTL_PKE)
+#define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 12)
+
+#define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 11)
+
+#define PAD_CTL_SPEED_LOW __MUX_PAD_CTRL(0 << 6)
+#define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(2 << 6)
+#define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 6)
+
+#define PAD_CTL_DSE_DISABLE __MUX_PAD_CTRL(0 << 3)
+#define PAD_CTL_DSE_240ohm __MUX_PAD_CTRL(1 << 3)
+#define PAD_CTL_DSE_120ohm __MUX_PAD_CTRL(2 << 3)
+#define PAD_CTL_DSE_80ohm __MUX_PAD_CTRL(3 << 3)
+#define PAD_CTL_DSE_60ohm __MUX_PAD_CTRL(4 << 3)
+#define PAD_CTL_DSE_48ohm __MUX_PAD_CTRL(5 << 3)
+#define PAD_CTL_DSE_40ohm __MUX_PAD_CTRL(6 << 3)
+#define PAD_CTL_DSE_34ohm __MUX_PAD_CTRL(7 << 3)
+
+#if defined CONFIG_SOC_MX6SL
+#define PAD_CTL_LVE __MUX_PAD_CTRL(1 << 1)
+#define PAD_CTL_LVE_BIT __MUX_PAD_CTRL(1 << 22)
+#endif
+
+#elif defined(CONFIG_SOC_VF610)
+
+#define PAD_MUX_MODE_SHIFT 20
+
+#define PAD_CTL_INPUT_DIFFERENTIAL __MUX_PAD_CTRL(1 << 16)
+
+#define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(1 << 12)
+#define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 12)
+
+#define PAD_CTL_SRE __MUX_PAD_CTRL(1 << 11)
+#define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 10)
+
+#define PAD_CTL_DSE_150ohm __MUX_PAD_CTRL(1 << 6)
+#define PAD_CTL_DSE_50ohm __MUX_PAD_CTRL(3 << 6)
+#define PAD_CTL_DSE_25ohm __MUX_PAD_CTRL(6 << 6)
+#define PAD_CTL_DSE_20ohm __MUX_PAD_CTRL(7 << 6)
+
+#define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 3)
+#define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 2 | PAD_CTL_PKE)
+
+#define PAD_CTL_OBE_IBE_ENABLE __MUX_PAD_CTRL(3 << 0)
+#define PAD_CTL_OBE_ENABLE __MUX_PAD_CTRL(1 << 1)
+#define PAD_CTL_IBE_ENABLE __MUX_PAD_CTRL(1 << 0)
+
+#else
+
+#define PAD_CTL_DVS __MUX_PAD_CTRL(1 << 13)
+#define PAD_CTL_INPUT_DDR __MUX_PAD_CTRL(1 << 9)
+#define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 8)
+
+#define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 7)
+#define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN __MUX_PAD_CTRL(0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 3)
+
+#define PAD_CTL_DSE_LOW __MUX_PAD_CTRL(0 << 1)
+#define PAD_CTL_DSE_MED __MUX_PAD_CTRL(1 << 1)
+#define PAD_CTL_DSE_HIGH __MUX_PAD_CTRL(2 << 1)
+#define PAD_CTL_DSE_MAX __MUX_PAD_CTRL(3 << 1)
+
+#endif
+
+#define PAD_CTL_SRE_SLOW __MUX_PAD_CTRL(0 << 0)
+#define PAD_CTL_SRE_FAST __MUX_PAD_CTRL(1 << 0)
+
+#define IOMUX_CONFIG_SION 0x10
+
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-#define MUX_CONFIG_SION (0x1 << 4)
-
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+void imx_iomux_v3_setup_pad(const iomux_v3_cfg_t pad);
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/*
+* Set bits for general purpose registers
+*/
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value);
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+ unsigned int direction);
+void imx_iomux_gpio_get_function(unsigned int gpio,
+ u32 *gpio_state);
+#endif
+
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_SOC_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def); \
+}
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
-#endif /* __MACH_IOMUX_V3_H__*/
+#endif /* __ASM_ARCH_IOMUX_V3_H__*/
projects / karo-tx-uboot.git / blobdiff