powerpc/mpc85xx: Add defines for serdes RSTCTL register

[karo-tx-uboot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index db70d048f5bed5d6f7501b4b1ed766d1eae67d44..db9f22025e9431a2d13991de1a7e6ae03932f669 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -6,23 +6,7 @@
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __IMMAP_85xx__
@@ -1560,6 +1544,18 @@ struct rio_pw {
 };
 #endif
 
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+struct rio_liodn {
+       u32     plbr;
+       u8      res0[28];
+       u32     plaor;
+       u8      res1[12];
+       u32     pludr;
+       u32     plldr;
+       u8      res2[456];
+};
+#endif
+
 /* RapidIO Registers */
 struct ccsr_rio {
        struct rio_arch arch;
@@ -1582,6 +1578,10 @@ struct ccsr_rio {
        u8      res7[100];
        struct rio_pw   pw;
 #endif
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+       u8      res5[8192];
+       struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+#endif
 };
 #endif
 
@@ -2542,7 +2542,9 @@ typedef struct serdes_corenet {
 #define SRDS_RSTCTL_RSTDONE    0x40000000
 #define SRDS_RSTCTL_RSTERR     0x20000000
 #define SRDS_RSTCTL_SWRST      0x10000000
-#define SRDS_RSTCTL_SDPD       0x00000020
+#define SRDS_RSTCTL_SDEN       0x00000020
+#define SRDS_RSTCTL_SDRST_B    0x00000040
+#define SRDS_RSTCTL_PLLRST_B   0x00000080
                u32     pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_POFF               0x80000000
 #define SRDS_PLLCR0_RFCK_SEL_MASK      0x70000000
@@ -3047,6 +3049,12 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET         0xE0000
 #define CONFIG_SYS_FSL_SRIO_OFFSET             0xC0000
 
+#if defined(CONFIG_BSC9132)
+#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET     0x10000
+#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
+       (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
+#endif
+
 #define CONFIG_SYS_FSL_CPC_ADDR        \
        (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
 #define CONFIG_SYS_FSL_QMAN_ADDR \