powerpc/b4860: Add workaround for errata A006384 and A006475

[karo-tx-uboot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 9b386ee6b2a6cb4d9ab65ae03feaa04f94c05827..edd7888c4c74a02db0929b88a0872bd0bdba6faa 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1621,6 +1621,8 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
 #define FSL_CORENET_DEVDISR2_10GEC1_1  0x00800000
 #define FSL_CORENET_DEVDISR2_10GEC1_2  0x00400000
+#define FSL_CORENET_DEVDISR2_10GEC1_3  0x80000000
+#define FSL_CORENET_DEVDISR2_10GEC1_4  0x40000000
 #define FSL_CORENET_DEVDISR2_DTSEC2_1  0x00080000
 #define FSL_CORENET_DEVDISR2_DTSEC2_2  0x00040000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3  0x00020000
@@ -1720,6 +1722,9 @@ typedef struct ccsr_gur {
        u32     rstrqpblsr;     /* Reset request preboot loader status */
        u8      res11[8];
        u32     rstrqmr1;       /* Reset request mask */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK      0x00000800
+#endif
        u8      res12[4];
        u32     rstrqsr1;       /* Reset request status */
        u8      res13[4];
@@ -1757,6 +1762,23 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  24
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL        0x00fe0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT  17
+#define FSL_CORENET_RCWSR13_EC1        0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII       0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO       0x10000000
+#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
+#define FSL_CORENET_RCWSR13_EC2        0x0c000000 /* bits 420..421 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII       0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO       0x10000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL      0x00000080
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH    0x00000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT    0x80000000
+#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL                0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT  16
+#define FSL_CORENET_RCWSR6_BOOT_LOC            0x0f800000
 #endif
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1        0x00800000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2        0x00400000
@@ -1766,6 +1788,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2        0x00040000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1        0x00020000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2        0x00010000
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK        0x00000011
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK      1
 
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT   17
@@ -1819,6 +1844,15 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII       0x00000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII       0x08000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO               0x10000000
+#endif
+#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define FSL_CORENET_RCWSR13_EC1                        0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII   0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO           0x40000000
+#define FSL_CORENET_RCWSR13_EC2                        0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII   0x00000000
+#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII  0x08000000
+#define FSL_CORENET_RCWSR13_EC2_GPIO           0x10000000
 #endif
        u8      res18[192];
        u32     scratchrw[4];   /* Scratch Read/Write */
@@ -2461,6 +2495,7 @@ typedef struct serdes_corenet {
 #define SRDS_RSTCTL_SDEN       0x00000020
 #define SRDS_RSTCTL_SDRST_B    0x00000040
 #define SRDS_RSTCTL_PLLRST_B   0x00000080
+#define SRDS_RSTCTL_RSTERR_SHIFT  29
                u32     pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_POFF               0x80000000
 #define SRDS_PLLCR0_RFCK_SEL_MASK      0x70000000
@@ -2470,6 +2505,7 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_RFCK_SEL_150       0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13    0x40000000
 #define SRDS_PLLCR0_RFCK_SEL_122_88    0x50000000
+#define SRDS_PLLCR0_DCBIAS_OUT_EN      0x02000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK     0x000f0000
 #define SRDS_PLLCR0_FRATE_SEL_5                0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_3_75     0x00050000
@@ -2477,9 +2513,22 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_FRATE_SEL_4                0x00070000
 #define SRDS_PLLCR0_FRATE_SEL_3_12     0x00090000
 #define SRDS_PLLCR0_FRATE_SEL_3                0x000a0000
+#define SRDS_PLLCR0_DCBIAS_OVRD                0x000000F0
+#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT  4
                u32     pllcr1; /* PLL Control Register 1 */
-#define SRDS_PLLCR1_PLL_BWSEL  0x08000000
-               u32     res_0c; /* 0x00c */
+#define SRDS_PLLCR1_BCAP_EN            0x20000000
+#define SRDS_PLLCR1_BCAP_OVD           0x10000000
+#define SRDS_PLLCR1_PLL_FCAP           0x001F8000
+#define SRDS_PLLCR1_PLL_FCAP_SHIFT     15
+#define SRDS_PLLCR1_PLL_BWSEL          0x08000000
+#define SRDS_PLLCR1_BYP_CAL            0x02000000
+               u32     pllsr2; /* At 0x00c, PLL Status Register 2 */
+#define SRDS_PLLSR2_BCAP_EN            0x00800000
+#define SRDS_PLLSR2_BCAP_EN_SHIFT      23
+#define SRDS_PLLSR2_FCAP               0x003F0000
+#define SRDS_PLLSR2_FCAP_SHIFT         16
+#define SRDS_PLLSR2_DCBIAS             0x000F0000
+#define SRDS_PLLSR2_DCBIAS_SHIFT       16
                u32     pllcr3;
                u32     pllcr4;
                u8      res_18[0x20-0x18];
@@ -2816,6 +2865,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CPC_OFFSET              0x10000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET         0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET         0x101000
+#define CONFIG_SYS_MPC85xx_DMA3_OFFSET         0x102000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET          CONFIG_SYS_MPC85xx_DMA1_OFFSET
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET         0x110000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET                0x114000