Merge git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / board / boundary / nitrogen6x / nitrogen6x.c

diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 1a29b6f4bd0639ff06aef6056b70b1ca83b421db..79ab44904e19a8ad293896c7fb2b3ef410b7ff3f 100644 (file)
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -461,25 +461,12 @@ struct display_info_t {
 static int detect_hdmi(struct display_info_t const *dev)
 {
        struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-       return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
+       return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
 }
 
-static void enable_hdmi(struct display_info_t const *dev)
+static void do_enable_hdmi(struct display_info_t const *dev)
 {
-       struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-       u8 reg;
-       printf("%s: setup HDMI monitor\n", __func__);
-       reg = readb(&hdmi->phy_conf0);
-       reg |= HDMI_PHY_CONF0_PDZ_MASK;
-       writeb(reg, &hdmi->phy_conf0);
-
-       udelay(3000);
-       reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
-       writeb(reg, &hdmi->phy_conf0);
-       udelay(3000);
-       reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
-       writeb(reg, &hdmi->phy_conf0);
-       writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+       imx_enable_hdmi_phy();
 }
 
 static int detect_i2c(struct display_info_t const *dev)
@@ -512,7 +499,7 @@ static struct display_info_t const displays[] = {{
        .addr   = 0,
        .pixfmt = IPU_PIX_FMT_RGB24,
        .detect = detect_hdmi,
-       .enable = enable_hdmi,
+       .enable = do_enable_hdmi,
        .mode   = {
                .name           = "HDMI",
                .refresh        = 60,
@@ -637,25 +624,15 @@ static void setup_display(void)
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-       struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-
        int reg;
 
+       enable_ipu_clock();
+       imx_setup_hdmi();
        /* Turn on LDB0,IPU,IPU DI0 clocks */
        reg = __raw_readl(&mxc_ccm->CCGR3);
-       reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
-               |MXC_CCM_CCGR3_LDB_DI0_MASK;
+       reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
        writel(reg, &mxc_ccm->CCGR3);
 
-       /* Turn on HDMI PHY clock */
-       reg = __raw_readl(&mxc_ccm->CCGR2);
-       reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
-              |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
-       writel(reg, &mxc_ccm->CCGR2);
-
-       /* clear HDMI PHY reset */
-       writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
-
        /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
        writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
        writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
@@ -673,15 +650,8 @@ static void setup_display(void)
        writel(reg, &mxc_ccm->cscmr2);
 
        reg = readl(&mxc_ccm->chsccdr);
-       reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
-               |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
-               |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
        reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-               <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
-             |(CHSCCDR_PODF_DIVIDE_BY_3
-               <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
-             |(CHSCCDR_IPU_PRE_CLK_540M_PFD
-               <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+               <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
        writel(reg, &mxc_ccm->chsccdr);
 
        reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES