board/b4860qds: Add support for configuring SerDes1 Refclks

[karo-tx-uboot.git] / board / freescale / b4860qds / eth_b4860qds.c

diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 19ca66e3d035a9122ac03c9e34e9cf62e26d9181..dc4ef80fc883f4ef85c57d2ca16499636d49b0ae 100644 (file)
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -201,8 +201,6 @@ int board_eth_init(bd_t *bis)
                debug("Setting phy addresses for FM1_DTSEC5: %x and"
                        "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
                        CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
                debug("Setting phy addresses for FM1_DTSEC5: %x and"
                        "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
                        CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);

-               /* Fixing Serdes clock by programming FPGA register */
-               QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);

                fm_info_set_phy_address(FM1_DTSEC5,
                                CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
                fm_info_set_phy_address(FM1_DTSEC6,
                fm_info_set_phy_address(FM1_DTSEC5,
                                CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
                fm_info_set_phy_address(FM1_DTSEC6,