karo: tx28: remove LCD pad configuration from SPL

[karo-tx-uboot.git] / board / karo / tx28 / spl_boot.c

diff --git a/board/karo/tx28/spl_boot.c b/board/karo/tx28/spl_boot.c
index 80fd25de6758a12e1825c98c818d47d5391aa26a..3c8d9db353a0070dd25018ff1dcb53ec41367fd6 100644 (file)
--- a/board/karo/tx28/spl_boot.c
+++ b/board/karo/tx28/spl_boot.c
@@ -43,41 +43,6 @@ static iomux_cfg_t tx28_stk5_pads[] = {
        /* LED */
        MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
 
-       /* framebuffer */
-       MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD,
-       MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD,
-
        /* DUART pads */
        MX28_PAD_PWM0__GPIO_3_16 | MUX_CONFIG_GPIO,
        MX28_PAD_PWM1__GPIO_3_17 | MUX_CONFIG_GPIO,
@@ -161,7 +126,7 @@ static iomux_cfg_t tx28_stk5_pads[] = {
        MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
        MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
        MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
-       MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_SSP0,
+       MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_GPIO,
        MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
 
        /* GPMI pads */
@@ -181,6 +146,11 @@ static iomux_cfg_t tx28_stk5_pads[] = {
        MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
        MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
 
+       /* maybe used for EDT-FT5x06 */
+       MX28_PAD_SSP0_DATA5__GPIO_2_5 | MUX_CONFIG_GPIO,
+       MX28_PAD_SSP0_DATA6__GPIO_2_6 | MUX_CONFIG_GPIO,
+       MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO,
+
        /* unused pads */
        MX28_PAD_GPMI_RDY1__GPIO_0_21 | MUX_CONFIG_GPIO,
        MX28_PAD_GPMI_RDY2__GPIO_0_22 | MUX_CONFIG_GPIO,
@@ -190,25 +160,26 @@ static iomux_cfg_t tx28_stk5_pads[] = {
        MX28_PAD_GPMI_CE3N__GPIO_0_19 | MUX_CONFIG_GPIO,
 
        MX28_PAD_SSP0_DATA4__GPIO_2_4 | MUX_CONFIG_GPIO,
-       MX28_PAD_SSP0_DATA5__GPIO_2_5 | MUX_CONFIG_GPIO,
-       MX28_PAD_SSP0_DATA6__GPIO_2_6 | MUX_CONFIG_GPIO,
        MX28_PAD_SSP0_DATA7__GPIO_2_7 | MUX_CONFIG_GPIO,
-};
 
+       MX28_PAD_SSP2_SS0__GPIO_2_19 | MUX_CONFIG_GPIO,
+       MX28_PAD_SSP2_SS1__GPIO_2_20 | MUX_CONFIG_GPIO,
+       MX28_PAD_SSP2_SS2__GPIO_2_21 | MUX_CONFIG_GPIO,
+       MX28_PAD_SSP3_SS0__GPIO_2_27 | MUX_CONFIG_GPIO,
 
-static void tx28_stk5_led_on(void)
-{
-       gpio_direction_output(MX28_PAD_ENET0_RXD3__GPIO_4_10, 1);
-}
+       MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO,
+       MX28_PAD_ENET0_TXD3__GPIO_4_12 | MUX_CONFIG_GPIO,
+       MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO,
+};
 
-void board_init_ll(void)
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
 {
-       mx28_common_spl_init(tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads));
-       tx28_stk5_led_on();
+       mxs_common_spl_init(arg, resptr,
+                       tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads));
 }
 
-#ifndef CONFIG_TX28_S
 static uint32_t tx28_dram_vals[] = {
+#ifdef CONFIG_TX28_S
        /* TX28-41x0: NT5TU32M16DG-AC */
        /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
        /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -216,8 +187,8 @@ static uint32_t tx28_dram_vals[] = {
        /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
        /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
        /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-       /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x01010101,
-       /* 070 */ 0x000f0f01, 0x0102020a, 0x00000000, 0x00010101,
+       /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x00010101,
+       /* 070 */ 0x000f0f01, 0x0102010a, 0x00000000, 0x00000101,
        /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002,
        /* 090 */ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
        /* 0a0 */ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
@@ -258,9 +229,7 @@ static uint32_t tx28_dram_vals[] = {
        /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004,
        /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000,
        /* 2f0 */ 0x00000000, 0x00000000,
-};
-#else
-static uint32_t tx28_dram_vals[] = {
+#elif CONFIG_SYS_SDRAM_SIZE == SZ_128M
        /* TX28-40x0: MT47H64M16HR-3 */
        /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
        /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -268,8 +237,8 @@ static uint32_t tx28_dram_vals[] = {
        /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
        /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
        /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-       /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x00010101,
-       /* 070 */ 0x000f0f01, 0x0102010a, 0x00000000, 0x00000101,
+       /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x01010101,
+       /* 070 */ 0x000f0f01, 0x0102020a, 0x00000000, 0x00010101,
        /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002,
        /* 090 */ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
        /* 0a0 */ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
@@ -310,13 +279,62 @@ static uint32_t tx28_dram_vals[] = {
        /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004,
        /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000,
        /* 2f0 */ 0x00000000, 0x00000000,
-};
+#elif CONFIG_SYS_SDRAM_SIZE == SZ_256M
+       /* TX28-40x2: MEM2G16D2DABG */
+       /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 020 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+       /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x01010101,
+       /* 070 */ 0x000f0f01, 0x0102010a, 0x00000000, 0x00010101,
+       /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002,
+       /* 090 */ 0x01010000, 0x07080603, 0x07005003, 0x0a0000c8,
+       /* 0a0 */ 0x02009c40, 0x0002030c, 0x00380e09, 0x0328063f,
+       /* 0b0 */ 0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
+       /* 0c0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+       /* 0d0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+       /* 0e0 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+       /* 0f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 100 */ 0x00000000, 0x00000000, 0x00000612, 0x01000102,
+       /* 110 */ 0x06120612, 0x00000200, 0x00020007, 0xf4002714,
+       /* 120 */ 0xf4002714, 0xf4002714, 0xf4002714, 0x07400300,
+       /* 130 */ 0x07400300, 0x07400300, 0x07400300, 0x00000005,
+       /* 140 */ 0x00000000, 0x00000000, 0x01000000, 0x01020408,
+       /* 150 */ 0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
+       /* 160 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+       /* 170 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+       /* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       /* 280 */ 0x00000000, 0x00000000, 0x00010000, 0x00030404,
+       /* 290 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+       /* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x01010000,
+       /* 2b0 */ 0x01000000, 0x03030000, 0x00010303, 0x01020202,
+       /* 2c0 */ 0x00000000, 0x02040303, 0x21002103, 0x00061200,
+       /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004,
+       /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000,
+       /* 2f0 */ 0x00000000, 0x00000000,
+#else
+#error No SDRAM configuration available
 #endif
+};
 
-void mx28_ddr2_setup(void)
+void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
-       int i;
-
-       for (i = 0; i < ARRAY_SIZE(tx28_dram_vals); i++)
-               writel(tx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
+       memcpy(dram_vals, tx28_dram_vals, sizeof(tx28_dram_vals));
 }