#include <config.h>
+#include <asm-offsets.h>
#include <configs/tx53.h>
+#include <linux/linkage.h>
#include <asm/arch/imx-regs.h>
#define DEBUG_LED_BIT 20
#define LED_MUX_MODE 0x11
#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
-
-#ifdef PHYS_SDRAM_2_SIZE
-#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-#else
-#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
-#endif
-
-#define REG_ESDCTL0 0x00
-#define REG_ESDCFG0 0x04
-#define REG_ESDCTL1 0x08
-#define REG_ESDCFG1 0x0c
-#define REG_ESDMISC 0x10
-#define REG_ESDSCR 0x14
-#define REG_ESDGPR 0x34
+#define SDRAM_SIZE (CONFIG_SYS_SDRAM_SIZE / SZ_1M)
#define REG_CCGR0 0x68
#define REG_CCGR1 0x6c
(((l) >> 8) & 0x0000FF00) | \
(((l) >> 24) & 0x000000FF))
-#define MXC_DCD_ITEM(addr, val) \
- .word CPU_2_BE_32(addr), CPU_2_BE_32(val)
+/*
+CCM register set 0x53FD4000 0x53FD7FFF
+EIM register set 0x63FDA000 0x63FDAFFF
+NANDFC register set 0xF7FF0000 0xF7FFFFFF
+IOMUX Control (IOMUXC) registers 0x53FA8000 0x53FABFFF
+DPLLC1 register 0x63F80000 0x63F83FFF
+DPLLC2 register 0x63F84000 0x63F87FFF
+DPLLC3 register 0x63F88000 0x63F8BFFF
+DPLLC4 register 0x63F8C000 0x63F8FFFF
+ESD RAM controller register 0x63FD9000 0x63FD9FFF
+M4IF register 0x63FD8000 0x63FD8FFF
+DDR 0x70000000 0xEFFFFFFF
+EIM 0xF0000000 0xF7FEFFFF
+NANDFC Buffers 0xF7FF0000 0xF7FFFFFF
+IRAM Free Space 0xF8006000 0xF8017FF0
+GPU Memory 0xF8020000 0xF805FFFF
+*/
+#define CHECK_DCD_ADDR(a) ( \
+ ((a) >= 0x53fd4000 && (a) <= 0x53fd7fff) /* CCM */ || \
+ ((a) >= 0x63fda000 && (a) <= 0x63fdafff) /* EIM (CS0) */ || \
+ ((a) >= 0x53fa8000 && (a) <= 0x53fabfff) /* IOMUXC */ || \
+ ((a) >= 0x63f80000 && (a) <= 0x63f8ffff) /* DPLLC1..4 */ || \
+ ((a) >= 0x63fd8000 && (a) <= 0x63fd9fff) /* M4IF & SDRAM Contr. */ || \
+ ((a) >= 0x70000000 && (a) <= 0xefffffff) /* SDRAM */ || \
+ ((a) >= 0xf0000000 && (a) <= 0xf7ffffff) /* EIM & NANDFC buffers */ || \
+ ((a) >= 0xf8006000 && (a) <= 0xf8017ff0) /* IRAM free space */ || \
+ ((a) >= 0xf8020000 && (a) <= 0xf805ffff) /* GPU RAM */)
+
+ .macro mxc_dcd_item addr, val
+ .ifne CHECK_DCD_ADDR(\addr)
+ .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
+ .else
+ .error "Address \addr not accessible from DCD"
+ .endif
+ .endm
+
+#define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_SZ_BYTE 1
#define MXC_DCD_CMD_SZ_SHORT 2
#define MXC_DCD_CMD_FLAG_WRITE 0x0
#define MXC_DCD_CMD_FLAG_CLR 0x1
#define MXC_DCD_CMD_FLAG_SET 0x3
-#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
-#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
-#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1))
-#define MXC_DCD_CMD_WRT(type, flags, next) \
- .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+#define MXC_DCD_START \
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
+dcd_start:
-#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
- .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+ .macro MXC_DCD_END
+1:
+ .ifgt . - dcd_start - 1768
+ .error "DCD too large!"
+ .endif
+dcd_end:
+ .section ".pad"
+ .section ".text"
+ .endm
+
+#define MXC_DCD_CMD_WRT(type, flags) \
+1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
CPU_2_BE_32(addr), CPU_2_BE_32(mask)
-#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
- .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
-#define MXC_DCD_CMD_NOP() \
- .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+#define MXC_DCD_CMD_NOP() \
+1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+#define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
+#define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100)
.macro CK_VAL, name, clks, offs, max
.iflt \clks - \offs
.else
.ifle \clks - \offs - \max
.set \name, \clks - \offs
+ .else
+ .error "Value \clks out of range for parameter \name"
.endif
.endif
.endm
#define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
/* DDR3 SDRAM */
-#if SDRAM_SIZE > RAM_BANK0_SIZE
-#define BANK_ADDR_BITS 2
-#else
-#define BANK_ADDR_BITS 1
-#endif
+#define BANK_ADDR_BITS CONFIG_NR_DRAM_BANKS
#define SDRAM_BURST_LENGTH 8
#define RALAT 5
-#define WALAT 1
+#define WALAT 0
+#define BI_ON 0
#define ADDR_MIRROR 0
#define DDR_TYPE ESDMISC_DDR_TYPE_DDR3
-/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+#if SDRAM_CLK > 666 && SDRAM_CLK <= 800
+#define CL_VAL 11
+#define CWL_VAL 8
+#elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
+#define CL_VAL 9 // or 10
+#define CWL_VAL 7
+#elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
+#define CL_VAL 7 // or 8
+#define CWL_VAL 6
+#elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
+#define CL_VAL 6
+#define CWL_VAL 5
+#elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
+#define CL_VAL 5
+#define CWL_VAL 5
+#else
+#error SDRAM clock out of range: 303 .. 800
+#endif
+
+#if SDRAM_SIZE < 2048
+/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
+
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
/* ESDCFG0 0x0c */
NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
-CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
-CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
-NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
-CK_VAL tCL, 9, 3, 8 /* clks - 3 (0..8) CAS Latency */
+NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
/* ESDCFG1 0x10 */
-NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
-NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
+CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
-NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
-CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
+CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */
+CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tCWL, 5, 2, 6 /* clks - 2 (0..6) */
+CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
/* ESDCFG2 0x14 */
CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
-CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
-CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
-CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */
/* ESDOR 0x30 */
CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#else
+/* 4096MiB SDRAM: IM4G16D3EABG-125I */
-/* ESDOTC 0x08 */
-NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
-NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
-CK_VAL tANPD, tCWL, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tAXPD, tCWL, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tODTLon tCWL - 1, 1, 7 /* clks - 1 (0..7) */
-CK_VAL tODTLoff tCWL - 1, 1, 31 /* clks - 1 (0..31) */
+#define ROW_ADDR_BITS 15
+#define COL_ADDR_BITS 10
-#define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
+/* ESDCFG0 0x0c */
+NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* ESDCFG1 0x10 */
+CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
+CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
+CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */
+CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */
+CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
+/* ESDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
+CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+
+/* ESDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#endif
+
+#define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
/* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
* erroneous Erratum Engcm12377
*/
#define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
-#define ROW_ADDR_BITS 14
-#define COL_ADDR_BITS 10
+/* ESDOTC 0x08 */
+CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
+CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
+CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */
+CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */
+
+/* ESDPDC 0x04 */
+CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7
+CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
+CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
+
+#define PRCT 0
+#define PWDT 5
+#define SLOW_PD 0
+#define BOTH_CS_PD 1
+
+#define ESDPDC_VAL_0 ( \
+ (PRCT << 28) | \
+ (PRCT << 24) | \
+ (tCKE << 16) | \
+ (SLOW_PD << 7) | \
+ (BOTH_CS_PD << 6) | \
+ (tCKSRX << 3) | \
+ (tCKSRE << 0) \
+ )
+
+#define ESDPDC_VAL_1 (ESDPDC_VAL_0 | \
+ (PWDT << 12) | \
+ (PWDT << 8) \
+ )
+
+#define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
+#define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
+#define DLL_DISABLE 0
.iflt tWR - 7
- .set mrs_val, (0x8080 | \
- (3 << 4) /* MRS command */ | \
- ((1 << 8) /* DLL Reset */ | \
- ((tWR + 1 - 4) << 9) | \
- (((tCL + 3) - 4) << 4)) << 16)
+ .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \
+ (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
+ ((tWR + 1 - 4) << 9) | \
+ ((((tCL + 3) - 4) & 0x7) << 4) | \
+ ((((tCL + 3) - 4) & 0x8) >> 1))
.else
- .set mrs_val, (0x8080 | \
- (3 << 4) /* MRS command */ | \
- ((1 << 8) /* DLL Reset */ | \
- (((tWR + 1) / 2) << 9) | \
- (((tCL + 3) - 4) << 4)) << 16)
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
+ (((tWR + 1) / 2) << 9) | \
+ ((((tCL + 3) - 4) & 0x7) << 4) | \
+ ((((tCL + 3) - 4) & 0x8) >> 1))
.endif
-#define ESDSCR_MRS_VAL(cs) (mrs_val | ((cs) << 3))
-
-#define ESDCFG0_VAL ( \
- (tRFC << 24) | \
- (tXS << 16) | \
- (tXP << 13) | \
- (tXPDLL << 9) | \
- (tFAW << 4) | \
- (tCL << 0)) \
-
-#define ESDCFG1_VAL ( \
- (tRCD << 29) | \
- (tRP << 26) | \
- (tRC << 21) | \
- (tRAS << 16) | \
- (tRPA << 15) | \
- (tWR << 9) | \
- (tMRD << 5) | \
- (tCWL << 0)) \
-
-#define ESDCFG2_VAL ( \
- (tDLLK << 16) | \
- (tRTP << 6) | \
- (tWTR << 3) | \
+
+#define mr1_val ( \
+ ((Rtt_Nom & 1) << 2) | \
+ (((Rtt_Nom >> 1) & 1) << 6) | \
+ (((Rtt_Nom >> 2) & 1) << 9) | \
+ (DLL_DISABLE << 0) | \
+ 0)
+#define mr2_val ( \
+ (Rtt_WR << 9) /* dynamic ODT */ | \
+ (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
+ (1 << 6) | /* ASR: Automatic Self Refresh */ \
+ (((tCWL + 2) - 5) << 3) | \
+ 0)
+#define mr3_val 0
+
+#define ESDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
+ (1 << 15) /* CON_REQ */ | \
+ 0x80 | \
+ (3 << 4) /* MRS command */ | \
+ ((cs) << 3) | \
+ ((mr) << 0) | \
+ 0)
+
+#define ESDCFG0_VAL ( \
+ (tRFC << 24) | \
+ (tXS << 16) | \
+ (tXP << 13) | \
+ (tXPDLL << 9) | \
+ (tFAW << 4) | \
+ (tCL << 0)) \
+
+#define ESDCFG1_VAL ( \
+ (tRCD << 29) | \
+ (tRP << 26) | \
+ (tRC << 21) | \
+ (tRAS << 16) | \
+ (tRPA << 15) | \
+ (tWR << 9) | \
+ (tMRD << 5) | \
+ (tCWL << 0)) \
+
+#define ESDCFG2_VAL ( \
+ (tDLLK << 16) | \
+ (tRTP << 6) | \
+ (tWTR << 3) | \
(tRRD << 0))
-#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
-#define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
- ((COL_ADDR_BITS - 9) << 20) | \
- (BURST_LEN << 19) | \
- (1 << 16) | /* SDRAM bus width */ \
- ((-1) << (32 - BANK_ADDR_BITS)))
+#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
-#define ESDMISC_VAL ((1 << 12) | \
- (0x3 << 9) | \
- (RALAT << 6) | \
- (WALAT << 16) | \
- (ADDR_MIRROR << 19) | \
- (DDR_TYPE << 3))
+#define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ (1 << 16) | /* SDRAM bus width */ \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+
+#define ESDMISC_VAL ((ADDR_MIRROR << 19) | \
+ (WALAT << 16) | \
+ (BI_ON << 12) | \
+ (0x3 << 9) | \
+ (RALAT << 6) | \
+ (DDR_TYPE << 3))
#define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
(tODTLon << 12) | \
(tODTLoff << 4))
-fcb_start:
- b _start
- .word 0x20424346 /* "FCB " marker */
- .word 0x01 /* FCB version number */
- .org 0x68
- .word 0x0 /* primary image starting page number */
- .word 0x0 /* secondary image starting page number */
- .word 0x6b
- .word 0x6b
- .word 0x0 /* DBBT start page (0 == NO DBBT) */
- .word 0 /* Bad block marker offset in main area (unused) */
- .org 0xac
- .word 0 /* BI Swap disabled */
- .word 0 /* Bad Block marker offset in spare area */
-fcb_end:
-
- .org 0x400
+ .section ".ivt"
ivt_header:
.word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
app_start_addr:
self_ptr:
.word ivt_header
app_code_csf:
+#ifdef CONFIG_SECURE_BOOT
+ .word __csf_data
+#else
.word 0x0
+#endif
.word 0x0
boot_data:
- .long fcb_start
+ .long CONFIG_SYS_TEXT_BASE
image_len:
- .long CONFIG_U_BOOT_IMG_SIZE
+ .long __uboot_img_len
plugin:
.word 0
ivt_end:
#define DCD_VERSION 0x40
dcd_hdr:
- .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
-dcd_start:
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+ MXC_DCD_START
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
+ MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V
+
/* disable all irrelevant clocks */
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR0, 0xffcf0fff)
- MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffc3)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffcf)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR2, 0x033c0000)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR3, 0x000000ff)
+#ifdef CONFIG_SECURE_BOOT
+ /* enable Sahara */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x0000c000)
+#else
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x00000000)
+#endif
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR5, 0x00fff033)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000)
MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a) /* CSCMR2 */
MXC_DCD_ITEM(0x53fd4024, 0x00080b18) /* CSCDR1 */
-#define DDR_SEL_VAL 2
-#define DSE_VAL 5
+#define DDR_SEL_VAL 0
+#define DSE_VAL 6
#define ODT_VAL 2
#define DDR_SEL_SHIFT 25
MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL)
MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL)
- MXC_DCD_ITEM(0x63fd9004, 0x00030012)
-
- /* MR0 - CS0 */
- MXC_DCD_ITEM(0x63fd901c, 0x00008032) /* MRS: MR2 */
- MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: MR3 */
- MXC_DCD_ITEM(0x63fd901c, 0x00408031) /* MRS: MR1 */
- MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0)) /* MRS: MR0 */
- /* MR0 - CS1 */
+ MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_0)
+
+ /* MR0..3 - CS0 */
+ MXC_DCD_ITEM(0x63fd901c, 0x00008000) /* CON_REQ */
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x63fd901c, 0x00004000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 2, mr2_val)) /* MRS: MR2 */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, mr3_val)) /* MRS: MR3 */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: MR1 */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 0, mr0_val)) /* MRS: MR0 */
#if BANK_ADDR_BITS > 1
- MXC_DCD_ITEM(0x63fd901c, 0x0000803a) /* MRS: MR2 */
- MXC_DCD_ITEM(0x63fd901c, 0x0000803b) /* MRS: MR3 */
- MXC_DCD_ITEM(0x63fd901c, 0x00408039) /* MRS: MR1 */
- MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1)) /* MRS: MR0 */
+ /* MR0..3 - CS1 */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 2, 0x0000)) /* MRS: MR2 */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 3, 0x0000)) /* MRS: MR3 */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 1, 0x0040)) /* MRS: MR1 */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 0, mr0_val)) /* MRS: MR0 */
#endif
- MXC_DCD_ITEM(0x63fd9020, 0x00005800) /* refresh interval */
- MXC_DCD_ITEM(0x63fd9058, 0x00011112)
+ MXC_DCD_ITEM(0x63fd9020, 3 << 14) /* disable refresh during calibration */
+ MXC_DCD_ITEM(0x63fd9058, 0x00022222)
MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */
MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */
MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */
-zq_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9040, 0x00010000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
-
- /* Write Leveling */
- MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
- MXC_DCD_ITEM(0x63fd901c, 0x00848231) /* MRS: start write leveling */
- MXC_DCD_ITEM(0x63fd901c, 0x00000000)
- MXC_DCD_ITEM(0x63fd9048, 0x00000001)
-wl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
- MXC_DCD_ITEM(0x63fd901c, 0x00048031) /* MRS: end write leveling */
- MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd9040, 0x00010000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
/* DQS calibration */
MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
- MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
-dqs_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
- MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd907c, 0x90000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
/* WR DL calibration */
- MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+ MXC_DCD_ITEM(0x63fd901c, 0x00008000)
MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
- MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
-wr_dl_calib: /* 6c4 */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
- MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a4, 0x00000010)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
/* RD DL calibration */
MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
- MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
-rd_dl_calib: /* 70c */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
- MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
- MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a0, 0x00000010)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+ MXC_DCD_ITEM(0x63fd9020, (3 << 11) | (0 << 14)) /* refresh interval: 4 cycles every 64kHz period */
+ MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_1)
- MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V
+ /* DDR calibration done */
+ MXC_DCD_ITEM(0x63fd901c, 0x00000000)
/* setup NFC pads */
/* MUX_SEL */
MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B
MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0
MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0
-dcd_end:
- .ifgt dcd_end - dcd_start - 1768
- DCD too large!
- .endif
+ MXC_DCD_END
projects / karo-tx-uboot.git / blobdiff