#define MMDC2_MPSWDRDR7 0x021b48b4
#endif
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
#define IOMUXC_GPR1 0x020e0004
#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e024c
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e02a8
#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
#endif
-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
#define IOMUXC_GPR1 0x020e0004
#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330
/* UART1 pad config */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */
#else
MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002) /* UART1 RXD INPUT_SEL */
/* DDRHYS */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
/* TERM_CTL[0..7] */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)