karo: tx6: try to revive I2C bus

[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 34a7b285e2178354ad3f95fe1dcb9330a65af212..1f140ecd9bf2344ee643a7c207466468592435a0 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -481,6 +481,8 @@ ivt_end:
 
 #ifdef CONFIG_SOC_MX6Q
 #define IOMUXC_GPR1                            0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e00a4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28       0x020e00c4
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e024c
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e02a8
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6                0x020e02ac
@@ -502,6 +504,9 @@ ivt_end:
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05      0x020e0310
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06      0x020e0314
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07      0x020e0318
+
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21       0x020e03b8
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28       0x020e03d8
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P     0x020e050c
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5                0x020e0510
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4                0x020e0514
@@ -570,12 +575,19 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_GRP_B4DS             0x020e07a0
 #define IOMUXC_SW_PAD_CTL_GRP_B5DS             0x020e07a4
 #define IOMUXC_SW_PAD_CTL_GRP_B6DS             0x020e07a8
+
 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT   0x020e091c
 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
+
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0898
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e089c
+#define TX6_I2C1_SEL_INP_VAL                   1
 #endif
 
 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 #define IOMUXC_GPR1                            0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e0158
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28       0x020e0174
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e0218
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e0330
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6                0x020e032c
@@ -597,6 +609,9 @@ ivt_end:
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05      0x020e0298
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06      0x020e029c
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07      0x020e02a0
+
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21       0x020e0528
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28       0x020e0544
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P     0x020e04d0
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5                0x020e0484
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4                0x020e0480
@@ -657,13 +672,26 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_GRP_B4DS             0x020e07a0
 #define IOMUXC_SW_PAD_CTL_GRP_B5DS             0x020e07a4
 #define IOMUXC_SW_PAD_CTL_GRP_B6DS             0x020e07a8
+
 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT   0x020e08f8
 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e08fc
+
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0868
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e086c
+#define TX6_I2C1_SEL_INP_VAL                   1
 #endif
 
 dcd_hdr:
        MXC_DCD_START
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+       /* setup I2C pads for PMIC */
+       MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21, 0x00000016)
+       MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28, 0x00000011)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, 0x0000f079)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, 0x0000f079)
+       MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, TX6_I2C1_SEL_INP_VAL)
+       MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, TX6_I2C1_SEL_INP_VAL)
+
        /* RESET_OUT GPIO_7_12 */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)