((PHYS_SDRAM_1_WIDTH / 32) << 16) | \
((-1) << (32 - BANK_ADDR_BITS)))
+#define MDMISC_WALAT(n) (((n) & 3) << 16)
+#define MDMISC_RALAT(n) (((n) & 7) << 6)
+
#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
- (WALAT << 16) | \
+ MDMISC_WALAT(WALAT) | \
(BI_ON << 12) | \
(0x3 << 9) | \
- (RALAT << 6) | \
+ MDMISC_RALAT(RALAT) | \
(DDR_TYPE << 3))
#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
#define MMDC1_MDRWD 0x021b002c
#define MMDC1_MDOR 0x021b0030
#define MMDC1_MDASP 0x021b0040
+
#define MMDC1_MAPSR 0x021b0404
+
#define MMDC1_MPZQHWCTRL 0x021b0800
#define MMDC1_MPWLGCR 0x021b0808
#define MMDC1_MPWLDECTRL0 0x021b080c
#if PHYS_SDRAM_1_WIDTH == 64
#define MMDC2_MDPDC 0x021b4004
+
#define MMDC2_MPWLGCR 0x021b4808
#define MMDC2_MPWLDECTRL0 0x021b480c
#define MMDC2_MPWLDECTRL1 0x021b4810
#define MMDC2_MPSWDRDR5 0x021b48ac
#define MMDC2_MPSWDRDR6 0x021b48b0
#define MMDC2_MPSWDRDR7 0x021b48b4
+#define MMDC2_MPMUR0 0x021b48b8
#endif
#ifdef CONFIG_SOC_MX6Q
#define IOMUXC_GPR1 0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e00a0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x020e0248
#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e024c
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e02a8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e02ac
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e02c0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e02c4
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x020e02c8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e02d4
#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e02d8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02dc
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0314
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e0318
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x020e03b4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e03b8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e03d8
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e050c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e05bc
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e05c0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e05c4
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x020e0618
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x020e061c
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x020e06b0
#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
#define IOMUXC_GPR1 0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e0154
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e0174
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x020e0214
#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e032c
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e0314
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e0318
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x020e031c
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e0270
#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e026c
#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02a8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e029c
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e02a0
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x020e0524
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e0528
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e0544
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e04d0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e0488
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e04d8
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e048c
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x020e05e4
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x020e05e8
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x020e0704
#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, TX6_I2C1_SEL_INP_VAL)
MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, TX6_I2C1_SEL_INP_VAL)
+ /* ENET_REF_CLK */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO16, 0x00000012)
+ /* ETN PHY nRST */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2, 0x00000015)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, 0x000030b0)
+ /* ETN PHY Power */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20, 0x00000015)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, 0x000030b0)
/* RESET_OUT GPIO_7_12 */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0)
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */
/* MDCTL */
MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
+#if BANK_ADDR_BITS > 1
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (3 << 30))
+#else
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (1 << 30))
+#endif
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL)
MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL)
MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0)
- MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_0)
MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)
/* CS0 MRS: */
/* DDR3 calibration */
MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
- MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001007)
+ MXC_DCD_ITEM(MMDC1_MAPSR, 1)
/* ZQ calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
#define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0)
/* Write leveling */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_RALAT(~0) | MDMISC_WALAT(~0)) /* increase WALAT/RALAT to max. */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+#define MPMUR_FRC_MSR (1 << 11)
+ MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
+ MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
#ifdef DO_DDR_CALIB
- MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
- MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
- MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, (1 << 30) | (1 << 28) | (0 << 23)) /* choose 32 wait cycles and start DQS calib. */
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_ANY_CLR, MMDC1_MPDGCTRL0, 0x10001000)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
#else /* DO_DDR_CALIB */
-#define MPMUR_FRC_MSR (1 << 11)
MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160)
MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f)
MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
+ MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
+ MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
#endif /* DO_DDR_CALIB */
+ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
/* DRAM_SDQS[0..7] pad config */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f)
MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f)
MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
+ MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
#endif /* DO_DDR_CALIB */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
#if BANK_ADDR_BITS > 1
#endif
MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
- MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006)
+ MXC_DCD_ITEM(MMDC1_MAPSR, (16 << 8))
MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
- MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1)
/* MDSCR: Normal operation */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)