#include <config.h>
+#include <asm-offsets.h>
#include <configs/tx6.h>
+#include <linux/linkage.h>
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
.endm
#define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
+#if PHYS_SDRAM_1_WIDTH == 16
+#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val)
+#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
+#else
+#define MXC_DCD_ITEM_16(addr, val)
+#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
+#endif
+#if PHYS_SDRAM_1_WIDTH > 16
+#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val)
+#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
+#else
+#define MXC_DCD_ITEM_32(addr, val)
+#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
+#endif
#if PHYS_SDRAM_1_WIDTH == 64
#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
.error "DCD too large!"
.endif
dcd_end:
+ .section ".pad"
+ .section ".text"
.endm
#define MXC_DCD_CMD_WRT(type, flags) \
(tODTLon << 12) | \
(tODTLoff << 4))
+ .section ".ivt"
ivt_header:
.word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
app_start_addr:
self_ptr:
.word ivt_header
app_code_csf:
+#ifdef CONFIG_SECURE_BOOT
+ .word __csf_data
+#else
.word 0x0
+#endif
.word 0x0
boot_data:
- .long _start
+ .long CONFIG_SYS_TEXT_BASE
image_len:
- .long CONFIG_U_BOOT_IMG_SIZE
+ .long __uboot_img_len
plugin:
.word 0
ivt_end:
#define DCD_VERSION 0x40
-#define CLKCTL_CCGR0 0x68
-#define CLKCTL_CCGR1 0x6c
-#define CLKCTL_CCGR2 0x70
-#define CLKCTL_CCGR3 0x74
-#define CLKCTL_CCGR4 0x78
-#define CLKCTL_CCGR5 0x7c
-#define CLKCTL_CCGR6 0x80
-#define CLKCTL_CCGR7 0x84
-#define CLKCTL_CMEOR 0x88
-
-#define DDR_SEL_VAL 3
-#define DSE_VAL 6
+#define DDR_SEL_VAL 3 /* DDR3 */
+#if PHYS_SDRAM_1_WIDTH == 16
+#define DSE1_VAL 6 /* Drive Strength for DATA lines */
+#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
+#else
+#define DSE1_VAL 6 /* Drive Strength for DATA lines */
+#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
+#endif
#define ODT_VAL 2
+#define DDR_PKE_VAL 0
#define DDR_SEL_SHIFT 18
#define DDR_MODE_SHIFT 17
#define PUS_SHIFT 14
#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
-#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
-#define DSE_MASK (DSE_VAL << DSE_SHIFT)
+#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) /* differential input mode */
+#define DSE1_MASK (DSE1_VAL << DSE_SHIFT)
+#define DSE2_MASK (DSE2_VAL << DSE_SHIFT)
#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+#define DDR_PKE_MASK (DDR_PKE_VAL << PKE_SHIFT)
-#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
-#define SDQS_MASK DSE_MASK
-#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
-#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
+#define DQM_MASK (DDR_MODE_MASK | DSE2_MASK)
+#define SDQS_MASK DSE2_MASK
+#define SDODT_MASK (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_MASK (DDR_MODE_MASK | DSE2_MASK)
#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
-#define DDR_ADDR_MASK 0
-#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
+#define DDR_ADDR_MASK (ODT_MASK | DDR_MODE_MASK)
+#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE2_MASK)
#define MMDC1_MDCTL 0x021b0000
#define MMDC1_MDPDC 0x021b0004
#define MMDC1_MPDGCTRL0 0x021b083c
#define MMDC1_MPDGCTRL1 0x021b0840
#define MMDC1_MPDGDLST0 0x021b0844
-#define MMDC1_MPWRDLST 0x021b0854
#define MMDC1_MPRDDLCTL 0x021b0848
#define MMDC1_MPRDDLST 0x021b084c
#define MMDC1_MPWRDLCTL 0x021b0850
#define MMDC2_MPSWDRDR7 0x021b48b4
#endif
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
#define IOMUXC_GPR1 0x020e0004
#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e024c
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e02a8
#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
#endif
-#ifdef CONFIG_MX6DL
+#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
#define IOMUXC_GPR1 0x020e0004
#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0754
-#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0758
#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e075c
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0760
#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
/* RESET_OUT GPIO_7_12 */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+ MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
+ MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
+ MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
/* IOMUX: */
MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
/* UART1 pad config */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */
#else
MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002) /* UART1 RXD INPUT_SEL */
/* DRAM_DQM[0..7] */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
/* DRAM_B[0..7]DS */
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
- MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
- MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
- MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
- MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE1_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE1_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE1_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE1_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE1_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE1_MASK)
/* ADDDS */
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK)
/* DDRMODE_CTL */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
/* DDRPKE */
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
/* DDRMODE */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
/* CTLDS */
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK)
/* DDR_TYPE */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
/* DDRPK */
/* DDRHYS */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
/* TERM_CTL[0..7] */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
/* MPRDDQBY[0..7]DL */
MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
- MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333)
- MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333)
+ MXC_DCD_ITEM_32(MMDC1_MPRDDQBY2DL, 0x33333333)
+ MXC_DCD_ITEM_32(MMDC1_MPRDDQBY3DL, 0x33333333)
MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
-#ifndef DO_WL_CALIB
#define WL_DLY_DQS_VAL 30
#define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS5 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0)
-#endif
/* Write leveling */
- MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
-#ifdef DO_WL_CALIB
- MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
- MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
-#endif /* PHYS_SDRAM_1_WIDTH == 64 */
-#else
MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
- MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
+ MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
-#endif /* DO_WL_CALIB */
-
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
- MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
-
+#if PHYS_SDRAM_1_WIDTH > 16
+#define DO_DDR_CALIB
+#endif
/* DQS gating calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
#if BANK_ADDR_BITS > 1
#endif
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
- MXC_DCD_ITEM(MMDC1_MPMUR0, 0x00000800)
+#ifdef DO_DDR_CALIB
MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
+#else /* DO_DDR_CALIB */
+#define MPMUR_FRC_MSR (1 << 11)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
+#endif /* DO_DDR_CALIB */
/* DRAM_SDQS[0..7] pad config */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
-
+#ifdef DO_DDR_CALIB
/* Read delay calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
+ MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000013)
+ MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
+#else /* DO_DDR_CALIB */
+ MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x4a4f4e4c)
+ MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x4e50504a)
+#endif /* DO_DDR_CALIB */
+#ifdef DO_DDR_CALIB
+ /* Write delay calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
+ MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
+ MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
#if PHYS_SDRAM_1_WIDTH == 64
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
#endif
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
+#else /* DO_DDR_CALIB */
+ MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f)
+ MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f)
+ MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
+#endif /* DO_DDR_CALIB */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
#if BANK_ADDR_BITS > 1
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
projects / karo-tx-uboot.git / blobdiff