#define DDR_SEL_VAL 3
#define DSE_VAL 6
#define ODT_VAL 2
+#define DDR_PKE_VAL 0
#define DDR_SEL_SHIFT 18
#define DDR_MODE_SHIFT 17
#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
#define DSE_MASK (DSE_VAL << DSE_SHIFT)
#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+#define DDR_PKE_MASK (DDR_PKE_VAL << PKE_SHIFT)
#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
#define SDQS_MASK DSE_MASK
#define MMDC1_MPDGCTRL0 0x021b083c
#define MMDC1_MPDGCTRL1 0x021b0840
#define MMDC1_MPDGDLST0 0x021b0844
-#define MMDC1_MPWRDLST 0x021b0854
#define MMDC1_MPRDDLCTL 0x021b0848
#define MMDC1_MPRDDLST 0x021b084c
#define MMDC1_MPWRDLCTL 0x021b0850
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0754
-#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0758
#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e075c
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0760
#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
/* DDRMODE_CTL */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
/* DDRPKE */
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
/* DDRMODE */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
/* CTLDS */