karo: tx6: fix definition of IOMUXC_SW_PAD_CTL_GRP_DDRPK for i.MX6DL

[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 95f0b6d9a90822100647eb9858f9ea5f89dca71d..3e1f7b73c0b66bb83da70a0fee478399a4b57302 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -3,8 +3,6 @@
 #include <asm/arch/imx-regs.h>
 #include <generated/asm-offsets.h>
 
 #include <asm/arch/imx-regs.h>
 #include <generated/asm-offsets.h>
 

-//#define DO_WL_CALIB
-

 #ifndef CCM_CCR
 #error asm-offsets not included
 #endif
 #ifndef CCM_CCR
 #error asm-offsets not included
 #endif


@@ -45,9 +43,9 @@
        .endif
        .endm
 
        .endif
        .endm
 

-#define MXC_DCD_ITEM(addr, val)                mxc_dcd_item    addr, val
+#define MXC_DCD_ITEM(addr, val)                mxc_dcd_item    (addr), (val)

 #if PHYS_SDRAM_1_WIDTH == 64
 #if PHYS_SDRAM_1_WIDTH == 64

-#define MXC_DCD_ITEM_64(addr, val)             mxc_dcd_item    addr, val
+#define MXC_DCD_ITEM_64(addr, val)             mxc_dcd_item    (addr), (val)

 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
 #else
 #define MXC_DCD_ITEM_64(addr, val)
 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
 #else
 #define MXC_DCD_ITEM_64(addr, val)


@@ -60,23 +58,37 @@
 #define MXC_DCD_CMD_FLAG_WRITE         0x0
 #define MXC_DCD_CMD_FLAG_CLR           0x1
 #define MXC_DCD_CMD_FLAG_SET           0x3
 #define MXC_DCD_CMD_FLAG_WRITE         0x0
 #define MXC_DCD_CMD_FLAG_CLR           0x1
 #define MXC_DCD_CMD_FLAG_SET           0x3

-#define MXC_DCD_CMD_FLAG_CHK_ANY       (1 << 0)
-#define MXC_DCD_CMD_FLAG_CHK_SET       (1 << 1)
-#define MXC_DCD_CMD_FLAG_CHK_CLR       (0 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR       ((0 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_SET       ((0 << 0) | (1 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_CLR   ((1 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_SET   ((1 << 0) | (1 << 1))
+
+#define MXC_DCD_START                                                  \
+       .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
+dcd_start:
+
+       .macro  MXC_DCD_END
+1:
+       .ifgt   . - dcd_start - 1768
+       .error  "DCD too large!"
+       .endif
+dcd_end:
+       .endm

 
 

-#define MXC_DCD_CMD_WRT(type, flags, next)                                     \
-       .word   CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+#define MXC_DCD_CMD_WRT(type, flags)                                   \
+1:     .word   CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))

 
 

-#define MXC_DCD_CMD_CHK(type, flags, addr, mask)                               \
-       .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask)                       \
+1:     .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \

                CPU_2_BE_32(addr), CPU_2_BE_32(mask)
 
                CPU_2_BE_32(addr), CPU_2_BE_32(mask)
 

-#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)                    \
-       .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)            \
+1:     .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \

                CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
 
                CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
 

-#define MXC_DCD_CMD_NOP()                                                      \
-       .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+#define MXC_DCD_CMD_NOP()                              \
+1:     .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+

 
 #define CK_TO_NS(ck)   (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
 #define NS_TO_CK(ns)   (((ns) * SDRAM_CLK + 999) / 1000)
 
 #define CK_TO_NS(ck)   (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
 #define NS_TO_CK(ns)   (((ns) * SDRAM_CLK + 999) / 1000)


@@ -339,6 +351,7 @@ ivt_end:
 #define DDR_SEL_VAL    3
 #define DSE_VAL                6
 #define ODT_VAL                2
 #define DDR_SEL_VAL    3
 #define DSE_VAL                6
 #define ODT_VAL                2

+#define DDR_PKE_VAL    0

 
 #define DDR_SEL_SHIFT  18
 #define DDR_MODE_SHIFT 17
 
 #define DDR_SEL_SHIFT  18
 #define DDR_MODE_SHIFT 17


@@ -353,6 +366,7 @@ ivt_end:
 #define DDR_MODE_MASK  (1 << DDR_MODE_SHIFT)
 #define DSE_MASK       (DSE_VAL << DSE_SHIFT)
 #define ODT_MASK       (ODT_VAL << ODT_SHIFT)
 #define DDR_MODE_MASK  (1 << DDR_MODE_SHIFT)
 #define DSE_MASK       (DSE_VAL << DSE_SHIFT)
 #define ODT_MASK       (ODT_VAL << ODT_SHIFT)

+#define DDR_PKE_MASK   (DDR_PKE_VAL << PKE_SHIFT)

 
 #define DQM_MASK       (DDR_MODE_MASK | DSE_MASK)
 #define SDQS_MASK      DSE_MASK
 
 #define DQM_MASK       (DDR_MODE_MASK | DSE_MASK)
 #define SDQS_MASK      DSE_MASK


@@ -388,7 +402,6 @@ ivt_end:
 #define MMDC1_MPDGCTRL0                                0x021b083c
 #define MMDC1_MPDGCTRL1                                0x021b0840
 #define MMDC1_MPDGDLST0                                0x021b0844
 #define MMDC1_MPDGCTRL0                                0x021b083c
 #define MMDC1_MPDGCTRL1                                0x021b0840
 #define MMDC1_MPDGDLST0                                0x021b0844

-#define MMDC1_MPWRDLST                         0x021b0854

 #define MMDC1_MPRDDLCTL                                0x021b0848
 #define MMDC1_MPRDDLST                         0x021b084c
 #define MMDC1_MPWRDLCTL                                0x021b0850
 #define MMDC1_MPRDDLCTL                                0x021b0848
 #define MMDC1_MPRDDLST                         0x021b084c
 #define MMDC1_MPWRDLCTL                                0x021b0850


@@ -612,7 +625,7 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS            0x020e074c
 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL      0x020e0750
 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE           0x020e0754
 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS            0x020e074c
 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL      0x020e0750
 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE           0x020e0754

-#define IOMUXC_SW_PAD_CTL_GRP_DDRPK            0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK            0x020e0758

 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS           0x020e075c
 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE          0x020e0760
 #define IOMUXC_SW_PAD_CTL_GRP_B0DS             0x020e0784
 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS           0x020e075c
 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE          0x020e0760
 #define IOMUXC_SW_PAD_CTL_GRP_B0DS             0x020e0784


@@ -624,14 +637,13 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_GRP_B4DS             0x020e07a0
 #define IOMUXC_SW_PAD_CTL_GRP_B5DS             0x020e07a4
 #define IOMUXC_SW_PAD_CTL_GRP_B6DS             0x020e07a8
 #define IOMUXC_SW_PAD_CTL_GRP_B4DS             0x020e07a0
 #define IOMUXC_SW_PAD_CTL_GRP_B5DS             0x020e07a4
 #define IOMUXC_SW_PAD_CTL_GRP_B6DS             0x020e07a8

-#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT   0x020e091c
-#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
+#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT   0x020e08f8
+#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e08fc

 #endif
 
 dcd_hdr:
 #endif
 
 dcd_hdr:

-       .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
-dcd_start:
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
+       MXC_DCD_START
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)

        /* RESET_OUT GPIO_7_12 */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
 
        /* RESET_OUT GPIO_7_12 */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
 


@@ -653,11 +665,16 @@ dcd_start:
        /* UART1 pad config */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
        /* UART1 pad config */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */

+#ifdef CONFIG_MX6Q

        MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
        MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */

+#else
+       MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002)        /* UART1 RXD INPUT_SEL */
+#endif

        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0,        0x00000001)        /* UART1 CTS */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1,        0x00000001)        /* UART1 RTS */
        MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT,   0x00000003)        /* UART1 RTS INPUT_SEL */
 
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0,        0x00000001)        /* UART1 CTS */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1,        0x00000001)        /* UART1 RTS */
        MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT,   0x00000003)        /* UART1 RTS INPUT_SEL */
 

+#ifdef CONFIG_NAND_MXS

        /* NAND */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE,    0x00000000)     /* NANDF_CLE: NANDF_CLE */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE,    0x00000000)     /* NANDF_ALE: NANDF_ALE */
        /* NAND */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE,    0x00000000)     /* NANDF_CLE: NANDF_CLE */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE,    0x00000000)     /* NANDF_ALE: NANDF_ALE */


@@ -674,7 +691,7 @@ dcd_start:
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000)     /* NANDF_D5: NANDF_D5 */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000)     /* NANDF_D6: NANDF_D6 */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000)     /* NANDF_D7: NANDF_D7 */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000)     /* NANDF_D5: NANDF_D5 */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000)     /* NANDF_D6: NANDF_D6 */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000)     /* NANDF_D7: NANDF_D7 */

-
+#endif

        /* ext. mem CS */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000)      /* NANDF_CS2: NANDF_CS2 */
        /* DRAM_DQM[0..7] */
        /* ext. mem CS */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000)      /* NANDF_CS2: NANDF_CS2 */
        /* DRAM_DQM[0..7] */


@@ -737,7 +754,7 @@ dcd_start:
        /* DDRMODE_CTL */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
        /* DDRPKE */
        /* DDRMODE_CTL */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
        /* DDRPKE */

-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)

        /* DDRMODE */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
        /* CTLDS */
        /* DDRMODE */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
        /* CTLDS */


@@ -772,30 +789,28 @@ dcd_start:
        MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
        /* MDMISC */
        MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
        MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
        /* MDMISC */
        MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */

-ddr_reset:

        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)

-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)

 
        /* MSDSCR Conf Req */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
 
        /* MSDSCR Conf Req */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)

-con_ack:

        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)

-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+

        /* MDCTL */
        MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
        /* MDCTL */
        MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)

-ddr_calib:

        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)

-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)

 
        MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
        MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
        MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
 
        MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
        MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
        MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)

-       MXC_DCD_ITEM(MMDC1_MDRWD,  0x000026d2) /* MDRWD */
+       MXC_DCD_ITEM(MMDC1_MDRWD,  0x000026d2)

        MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
        MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
        MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
        MXC_DCD_ITEM_64(MMDC2_MDPDC,  MDPDC_VAL_0)
        MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
        MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
        MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
        MXC_DCD_ITEM_64(MMDC2_MDPDC,  MDPDC_VAL_0)

-       MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */
+       MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)

 
        /* CS0 MRS: */
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
 
        /* CS0 MRS: */
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))


@@ -803,34 +818,33 @@ ddr_calib:
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
 #if BANK_ADDR_BITS > 1
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
 #if BANK_ADDR_BITS > 1

-       /* CS1 MRS: MR2 */
+       /* CS1 MRS: */

        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))

-       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))

 #endif
 
        MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
 #endif
 
        MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */

+       MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */

 
 

-       MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222) /* MPODTCTRL */
+       MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222)

        MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
 
        /* DDR3 calibration */
        MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
        MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
 
        /* DDR3 calibration */
        MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */

-       MXC_DCD_ITEM(MMDC1_MAPSR,     0x00011007)
+       MXC_DCD_ITEM(MMDC1_MAPSR,     0x00001007)

 
        /* ZQ calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
 
        /* ZQ calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */

-       MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b)
+       MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)

 
 

-zq_calib:

        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)

-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)

 
        MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
 
 
        MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
 

-#ifndef DO_WL_CALIB

 #define WL_DLY_DQS_VAL 30
 #define WL_DLY_DQS0    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS1    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS_VAL 30
 #define WL_DLY_DQS0    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS1    (WL_DLY_DQS_VAL + 0)


@@ -840,33 +854,17 @@ zq_calib:
 #define WL_DLY_DQS5    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS6    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS7    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS5    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS6    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS7    (WL_DLY_DQS_VAL + 0)

-#endif

        /* Write leveling */
        /* Write leveling */

-       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
-#ifdef DO_WL_CALIB
-       MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
-       MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
-wl_calib:
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
-#if PHYS_SDRAM_1_WIDTH == 64
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
-#endif /* PHYS_SDRAM_1_WIDTH == 64 */
-#else

        MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
        MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
        MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
        MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))

-wl_calib:
-#endif /* DO_WL_CALIB */
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
-
-       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
-
-       MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)

 
        /* DQS gating calibration */
 
        /* DQS gating calibration */

+       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
+#if BANK_ADDR_BITS > 1
+       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+#endif

        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)


@@ -876,8 +874,6 @@ wl_calib:
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
 
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
 

-       MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
-

        MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
 
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
 


@@ -887,18 +883,14 @@ wl_calib:
        MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
        MXC_DCD_ITEM(MMDC1_MPMUR0,    0x00000800)
        MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
        MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
        MXC_DCD_ITEM(MMDC1_MPMUR0,    0x00000800)
        MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */

-dqs_fifo_reset:

        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)

-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)

        MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
        MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */

-dqs_fifo_reset2:

        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)

-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)

        MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
        MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */

-dqs_calib:
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)

 
        /* DRAM_SDQS[0..7] pad config */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
 
        /* DRAM_SDQS[0..7] pad config */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)


@@ -909,47 +901,38 @@ dqs_calib:
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)

-       MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)

 
        /* Read delay calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
        MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
        MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
 
        /* Read delay calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
        MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
        MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */

-rd_dl_calib:
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f)
-       MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
-       MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
+       MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)

 
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
        MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
 
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
        MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */

-wr_dl_calib:
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f)
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)

 #if PHYS_SDRAM_1_WIDTH == 64
 #if PHYS_SDRAM_1_WIDTH == 64

-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib2)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)

 
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
        MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
 
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
        MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */

-wr_dl_calib2:
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f)
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)

 #endif
 #endif

-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)

 
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
 
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */

+#if BANK_ADDR_BITS > 1
+       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
+#endif
+       MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)

        MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
        MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */

-       MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011006) /* MAPSR */
+       MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006)

        MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
        MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1)
 
        /* MDSCR: Normal operation */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
        MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
        MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1)
 
        /* MDSCR: Normal operation */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)

-
-con_ack_clr:

        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)

-dcd_end:
-       .ifgt   dcd_end - dcd_start - 1768
-       .error  "DCD too large!"
-       .endif
+       MXC_DCD_END