karo: tx6: increase WALAT/RALAT to max. during DDR calibration

[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 11189e11c1d2147746519f94c087721fac12b96c..6953b7b45fd624b9fb00662a7a72987f77ccfd18 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -1,5 +1,7 @@
 #include <config.h>
+#include <asm-offsets.h>
 #include <configs/tx6.h>
+#include <linux/linkage.h>
 #include <asm/arch/imx-regs.h>
 #include <generated/asm-offsets.h>
 
@@ -87,6 +89,8 @@ dcd_start:
        .error  "DCD too large!"
        .endif
 dcd_end:
+       .section ".pad"
+       .section ".text"
        .endm
 
 #define MXC_DCD_CMD_WRT(type, flags)                                   \
@@ -313,11 +317,14 @@ CK_MAX    tCKSRE, NS_TO_CK(10), 5, 0, 7
                                ((PHYS_SDRAM_1_WIDTH / 32) << 16) |     \
                                ((-1) << (32 - BANK_ADDR_BITS)))
 
+#define MDMISC_WALAT(n)                (((n) & 3) << 16)
+#define MDMISC_RALAT(n)                (((n) & 7) << 6)
+
 #define MDMISC_VAL             ((ADDR_MIRROR << 19) |  \
-                               (WALAT << 16) |         \
+                               MDMISC_WALAT(WALAT) |   \
                                (BI_ON << 12) |         \
                                (0x3 << 9) |            \
-                               (RALAT << 6) |          \
+                               MDMISC_RALAT(RALAT) |   \
                                (DDR_TYPE << 3))
 
 #define MDOR_VAL               ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
@@ -329,6 +336,7 @@ CK_MAX      tCKSRE, NS_TO_CK(10), 5, 0, 7
                                (tODTLon << 12) |       \
                                (tODTLoff << 4))
 
+       .section ".ivt"
 ivt_header:
        .word   CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
 app_start_addr:
@@ -341,12 +349,16 @@ boot_data_ptr:
 self_ptr:
        .word   ivt_header
 app_code_csf:
+#ifdef CONFIG_SECURE_BOOT
+       .word   __csf_data
+#else
        .word   0x0
+#endif
        .word   0x0
 boot_data:
-       .long   _start
+       .long   CONFIG_SYS_TEXT_BASE
 image_len:
-       .long   CONFIG_U_BOOT_IMG_SIZE
+       .long   __uboot_img_len
 plugin:
        .word   0
 ivt_end:
@@ -470,8 +482,10 @@ ivt_end:
 #define MMDC2_MPSWDRDR7                                0x021b48b4
 #endif
 
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
 #define IOMUXC_GPR1                            0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e00a4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28       0x020e00c4
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e024c
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e02a8
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6                0x020e02ac
@@ -493,6 +507,9 @@ ivt_end:
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05      0x020e0310
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06      0x020e0314
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07      0x020e0318
+
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21       0x020e03b8
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28       0x020e03d8
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P     0x020e050c
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5                0x020e0510
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4                0x020e0514
@@ -561,12 +578,19 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_GRP_B4DS             0x020e07a0
 #define IOMUXC_SW_PAD_CTL_GRP_B5DS             0x020e07a4
 #define IOMUXC_SW_PAD_CTL_GRP_B6DS             0x020e07a8
+
 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT   0x020e091c
 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
+
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0898
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e089c
+#define TX6_I2C1_SEL_INP_VAL                   1
 #endif
 
-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 #define IOMUXC_GPR1                            0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e0158
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28       0x020e0174
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e0218
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e0330
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6                0x020e032c
@@ -588,6 +612,9 @@ ivt_end:
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05      0x020e0298
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06      0x020e029c
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07      0x020e02a0
+
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21       0x020e0528
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28       0x020e0544
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P     0x020e04d0
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5                0x020e0484
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4                0x020e0480
@@ -648,17 +675,32 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_GRP_B4DS             0x020e07a0
 #define IOMUXC_SW_PAD_CTL_GRP_B5DS             0x020e07a4
 #define IOMUXC_SW_PAD_CTL_GRP_B6DS             0x020e07a8
+
 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT   0x020e08f8
 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e08fc
+
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0868
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e086c
+#define TX6_I2C1_SEL_INP_VAL                   1
 #endif
 
 dcd_hdr:
        MXC_DCD_START
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+       /* setup I2C pads for PMIC */
+       MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21, 0x00000016)
+       MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28, 0x00000011)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, 0x0000f079)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, 0x0000f079)
+       MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, TX6_I2C1_SEL_INP_VAL)
+       MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, TX6_I2C1_SEL_INP_VAL)
+
        /* RESET_OUT GPIO_7_12 */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
 
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
 
        MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
 
@@ -670,13 +712,16 @@ dcd_hdr:
        MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
        MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
        MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+       MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
+       MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
+       MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
 
        /* IOMUX: */
        MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
        /* UART1 pad config */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
        MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
 #else
        MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002)        /* UART1 RXD INPUT_SEL */
@@ -777,7 +822,7 @@ dcd_hdr:
        /* DDRHYS */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
 
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
        /* TERM_CTL[0..7] */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
@@ -820,7 +865,6 @@ dcd_hdr:
        MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
        MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
        MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
-       MXC_DCD_ITEM_64(MMDC2_MDPDC,  MDPDC_VAL_0)
        MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)
 
        /* CS0 MRS: */
@@ -866,6 +910,10 @@ dcd_hdr:
 #define WL_DLY_DQS6    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS7    (WL_DLY_DQS_VAL + 0)
        /* Write leveling */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+       MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_RALAT(~0) | MDMISC_WALAT(~0)) /* increase WALAT/RALAT to max. */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
        MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
        MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
@@ -912,6 +960,7 @@ dcd_hdr:
        MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
        MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
 #endif /* DO_DDR_CALIB */
+       MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
        /* DRAM_SDQS[0..7] pad config */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
@@ -961,7 +1010,6 @@ dcd_hdr:
        MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
        MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006)
        MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
-       MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1)
 
        /* MDSCR: Normal operation */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)