.endm
#define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
+#if PHYS_SDRAM_1_WIDTH == 16
+#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val)
+#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
+#else
+#define MXC_DCD_ITEM_16(addr, val)
+#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
+#endif
+#if PHYS_SDRAM_1_WIDTH > 16
+#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val)
+#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
+#else
+#define MXC_DCD_ITEM_32(addr, val)
+#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
+#endif
#if PHYS_SDRAM_1_WIDTH == 64
#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#define DDR_SEL_VAL 3
#define DSE_VAL 6
#define ODT_VAL 2
+#define DDR_PKE_VAL 0
#define DDR_SEL_SHIFT 18
#define DDR_MODE_SHIFT 17
#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
#define DSE_MASK (DSE_VAL << DSE_SHIFT)
#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+#define DDR_PKE_MASK (DDR_PKE_VAL << PKE_SHIFT)
#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
#define SDQS_MASK DSE_MASK
#define MMDC1_MPDGCTRL0 0x021b083c
#define MMDC1_MPDGCTRL1 0x021b0840
#define MMDC1_MPDGDLST0 0x021b0844
-#define MMDC1_MPWRDLST 0x021b0854
#define MMDC1_MPRDDLCTL 0x021b0848
#define MMDC1_MPRDDLST 0x021b084c
#define MMDC1_MPWRDLCTL 0x021b0850
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0754
-#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0758
#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e075c
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0760
#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1, 0x00000001) /* UART1 RTS */
MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */
+#ifdef CONFIG_NAND_MXS
/* NAND */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
-
+#endif
/* ext. mem CS */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
/* DRAM_DQM[0..7] */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
/* DRAM_B[0..7]DS */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
/* DDRMODE_CTL */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
/* DDRPKE */
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
/* DDRMODE */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
/* CTLDS */
/* MPRDDQBY[0..7]DL */
MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
- MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333)
- MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333)
+ MXC_DCD_ITEM_32(MMDC1_MPRDDQBY2DL, 0x33333333)
+ MXC_DCD_ITEM_32(MMDC1_MPRDDQBY3DL, 0x33333333)
MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
/* MDCTL */
MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
- MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2) /* MDRWD */
+ MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2)
MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL)
MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL)
MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0)
MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_0)
- MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */
+ MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)
/* CS0 MRS: */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
#if BANK_ADDR_BITS > 1
- /* CS1 MRS: MR2 */
+ /* CS1 MRS: */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
- MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
#endif
MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
- MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222) /* MPODTCTRL */
+ MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222)
MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
/* DDR3 calibration */
/* ZQ calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
- MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b)
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
-#ifndef DO_WL_CALIB
#define WL_DLY_DQS_VAL 30
#define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS5 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0)
#define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0)
-#endif
/* Write leveling */
- MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
-#ifdef DO_WL_CALIB
- MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
- MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
-#endif /* PHYS_SDRAM_1_WIDTH == 64 */
-#else
MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
- MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
+ MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
-#endif /* DO_WL_CALIB */
-
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
- MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
-
- MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
+#if PHYS_SDRAM_1_WIDTH > 16
+#define DO_DDR_CALIB
+#endif
/* DQS gating calibration */
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
+#if BANK_ADDR_BITS > 1
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+#endif
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
-
MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
- MXC_DCD_ITEM(MMDC1_MPMUR0, 0x00000800)
+#ifdef DO_DDR_CALIB
MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
+#else /* DO_DDR_CALIB */
+#define MPMUR_FRC_MSR (1 << 11)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
+#endif /* DO_DDR_CALIB */
/* DRAM_SDQS[0..7] pad config */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
+ MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
- MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
-
+#ifdef DO_DDR_CALIB
/* Read delay calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f)
- MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
- MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
+ MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
+#else /* DO_DDR_CALIB */
+ MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x4a4f4e4c)
+ MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x4e50504a)
+#endif /* DO_DDR_CALIB */
+#ifdef DO_DDR_CALIB
+ /* Write delay calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
#if PHYS_SDRAM_1_WIDTH == 64
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
#endif
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
+#else /* DO_DDR_CALIB */
+ MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f)
+ MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f)
+ MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
+#endif /* DO_DDR_CALIB */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+#if BANK_ADDR_BITS > 1
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
+#endif
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006)
MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
projects / karo-tx-uboot.git / blobdiff