u8 val;
u8 mask;
} rn5t618_regs[] = {
+#if CONFIG_TX6_REV == 2
{ RN5T618_NOETIMSET, 0, },
{ RN5T618_DC1DAC, VDD_CORE_VAL, },
{ RN5T618_DC2DAC, VDD_SOC_VAL, },
{ RN5T618_LDO3DAC, VDD_HIGH_VAL, },
{ RN5T618_LDORTCDAC, VDD_RTC_VAL, },
{ RN5T618_LDORTC1_SLOT, 0x0f, ~0x3f, },
+#elif CONFIG_TX6_REV == 3
+ { RN5T618_NOETIMSET, 0, },
+ { RN5T618_DC1DAC, VDD_CORE_VAL, },
+ { RN5T618_DC2DAC, VDD_SOC_VAL, },
+ { RN5T618_DC3DAC, VDD_DDR_VAL, },
+ { RN5T618_DC1DAC_SLP, VDD_CORE_VAL_LP, },
+ { RN5T618_DC2DAC_SLP, VDD_SOC_VAL_LP, },
+ { RN5T618_DC3DAC_SLP, VDD_DDR_VAL_LP, },
+ { RN5T618_LDOEN1, 0x01f, ~0x1f, },
+ { RN5T618_LDOEN2, 0x10, ~0x30, },
+ { RN5T618_LDODIS, 0x00, },
+ { RN5T618_LDO3DAC, VDD_HIGH_VAL, },
+ { RN5T618_LDORTCDAC, VDD_RTC_VAL, },
+ { RN5T618_LDORTC1_SLOT, 0x0f, ~0x3f, },
+#else
+#error Unsupported TX6 module revision
+#endif
};
static int rn5t618_setup_regs(struct rn5t618_regs *r, size_t count)