PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_34ohm | \
PAD_CTL_SRE_FAST)
-#define TX6UL_I2C_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
- PAD_CTL_HYS | \
- PAD_CTL_DSE_34ohm | \
- PAD_CTL_SPEED_MED)
#define TX6UL_ENET_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_48ohm | \
+ PAD_CTL_DSE_120ohm | \
PAD_CTL_PUS_100K_UP | \
PAD_CTL_SRE_FAST)
#define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
/* FEC functions */
- MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
- PAD_CTL_SPEED_MED),
+ MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm |
+ PAD_CTL_SPEED_LOW),
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
- PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED),
- MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
- MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST),
+ PAD_CTL_DSE_120ohm |
+ PAD_CTL_SPEED_LOW),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
+ PAD_CTL_DSE_80ohm |
+ PAD_CTL_SRE_SLOW),
+
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
};
static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
- MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
- MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
+ MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
+ PAD_CTL_DSE_80ohm |
+ PAD_CTL_SRE_SLOW),
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
TX6UL_I2C_PAD_CTRL, /* I2C SDA */
};
-static const iomux_v3_cfg_t const tx6ul_i2c_gpio_pads[] = {
- /* internal I2C set up for I2C bus recovery */
- MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
- TX6UL_I2C_PAD_CTRL, /* I2C SCL */
- MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
- TX6UL_I2C_PAD_CTRL, /* I2C SDA */
-};
-
static const struct gpio const tx6ul_gpios[] = {
#ifdef CONFIG_SYS_I2C_SOFT
/* These two entries are used to forcefully reinitialize the I2C bus */
struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
- (readl(&sda_regs->gpio_psr) & SDA_BIT))
+ (readl(&sda_regs->gpio_psr) & SDA_BIT))
return;
debug("Clearing I2C bus\n");
setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
- MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
+ MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
}
if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
printf("I2C SDA stuck LOW\n");
setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
- imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_gpio_pads,
- ARRAY_SIZE(tx6ul_i2c_gpio_pads));
-
udelay(5);
for (i = 0; i < 18; i++) {
printf("I2C bus recovery succeeded\n");
} else {
printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
- scl, sda);
+ scl, sda);
}
imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
- ARRAY_SIZE(tx6ul_i2c_pads));
+ ARRAY_SIZE(tx6ul_i2c_pads));
}
}
#else
cpu_str = "Q";
else if (is_cpu_type(MXC_CPU_MX6UL))
cpu_str = "UL";
+ else if (is_cpu_type(MXC_CPU_MX6ULL))
+ cpu_str = "ULL";
printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
cpu_str,
static inline u8 tx6ul_mem_suffix(void)
{
-#ifdef CONFIG_TX6_NAND
- return '0';
-#else
- return '1';
-#endif
+ return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
+ IS_ENABLED(CONFIG_TX6_EMMC);
}
#ifdef CONFIG_RN5T567
{
int ret;
u32 cpurev = get_cpu_rev();
+ char f = '?';
- debug("%s@%d: \n", __func__, __LINE__);
+ if (is_cpu_type(MXC_CPU_MX6UL))
+ f = ((cpurev & 0xf0) > 0x10) ? '5' : '0';
+ else if (is_cpu_type(MXC_CPU_MX6ULL))
+ f = '8';
+
+ debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
- printf("Board: Ka-Ro TXUL-%c01%c\n",
- ((cpurev &0xff) > 0x10) ? '5' : '0',
- tx6ul_mem_suffix());
+ printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
get_hab_status();
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
+ PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
return 0;
}
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
+ PHYS_SDRAM_1_SIZE);
#if CONFIG_NR_DRAM_BANKS > 1
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
- PHYS_SDRAM_2_SIZE);
+ PHYS_SDRAM_2_SIZE);
#endif
}
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
/* eMMC RESET */
MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
- PAD_CTL_DSE_40ohm),
+ PAD_CTL_DSE_40ohm),
};
#endif
return 1;
debug("SD card %d is %spresent (GPIO %d)\n",
- cfg - tx6ul_esdhc_cfg,
- gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
- cfg->cd_gpio);
+ cfg - tx6ul_esdhc_cfg,
+ gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
+ cfg->cd_gpio);
return !gpio_get_value(cfg->cd_gpio);
}
if (cfg->cd_gpio >= 0) {
ret = gpio_request_one(cfg->cd_gpio,
- GPIOFLAG_INPUT, "MMC CD");
+ GPIOFLAG_INPUT, "MMC CD");
if (ret) {
printf("Error %d requesting GPIO%d_%d\n",
- ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
+ ret, cfg->cd_gpio / 32,
+ cfg->cd_gpio % 32);
continue;
}
}
{ IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
};
+static const iomux_v3_cfg_t tx_tester_pads[] = {
+ /* SW controlled LEDs on TX-TESTER-V5 baseboard */
+ MX6_PAD_SNVS_TAMPER4__GPIO5_IO04, /* red LED */
+ MX6_PAD_SNVS_TAMPER9__GPIO5_IO09, /* yellow LED */
+ MX6_PAD_SNVS_TAMPER8__GPIO5_IO08, /* green LED */
+
+ MX6_PAD_LCD_DATA04__GPIO3_IO09, /* IO_RESET */
+
+ /* I2C bus on DIMM pins 40/41 */
+ MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
+ MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
+
+ /* USBH1 */
+ MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
+ MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
+
+ /* USBOTG */
+ MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
+ MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
+
+ MX6_PAD_LCD_DATA08__GPIO3_IO13 | TX6UL_GPIO_OUT_PAD_CTRL,
+ MX6_PAD_LCD_DATA09__GPIO3_IO14 | TX6UL_GPIO_OUT_PAD_CTRL,
+ MX6_PAD_LCD_DATA10__GPIO3_IO15 | TX6UL_GPIO_OUT_PAD_CTRL,
+
+ /* USBH_VBUSEN */
+ MX6_PAD_LCD_DATA11__GPIO3_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
+
+ /*
+ * no drive capability for DUT_ETN_LINKLED, DUT_ETN_ACTLED
+ * to not interfere whith the DUT ETN PHY strap pins
+ */
+ MX6_PAD_SNVS_TAMPER2__GPIO5_IO02, MUX_PAD_CTRL(PAD_CTL_HYS |
+ PAD_CTL_DSE_DISABLE |
+ PAD_CTL_SPEED_LOW),
+ MX6_PAD_SNVS_TAMPER3__GPIO5_IO03, MUX_PAD_CTRL(PAD_CTL_HYS |
+ PAD_CTL_DSE_DISABLE |
+ PAD_CTL_SPEED_LOW),
+};
+
+static const struct gpio tx_tester_gpios[] = {
+ { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LEDGE#", },
+ { IMX_GPIO_NR(5, 4), GPIOFLAG_OUTPUT_INIT_LOW, "LEDRT#", },
+ { IMX_GPIO_NR(5, 8), GPIOFLAG_OUTPUT_INIT_LOW, "LEDGN#", },
+
+ { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_HIGH, "PMIC PWR_ON", },
+
+ { IMX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "TSTART#", },
+ { IMX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "STARTED", },
+ { IMX_GPIO_NR(3, 7), GPIOFLAG_INPUT, "TSTOP#", },
+ { IMX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "STOP#", },
+
+ { IMX_GPIO_NR(3, 10), GPIOFLAG_INPUT, "DUT_PGOOD", },
+
+ { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_HIGH, "VBACKUP_OFF", },
+ { IMX_GPIO_NR(3, 12), GPIOFLAG_OUTPUT_INIT_LOW, "VBACKUP_LOAD", },
+
+ { IMX_GPIO_NR(1, 10), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD1", },
+ { IMX_GPIO_NR(3, 30), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD2", },
+ { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD3", },
+
+ { IMX_GPIO_NR(3, 13), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD1", },
+ { IMX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD2", },
+ { IMX_GPIO_NR(3, 15), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD3", },
+};
+
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
/* set to max. size supported by SoC */
gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
udelay(300000);
gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
- lcd_backlight_polarity());
+ lcd_backlight_polarity());
}
}
if (fb_mode.xres > panel_info.vl_col ||
fb_mode.yres > panel_info.vl_row) {
printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
- fb_mode.xres, fb_mode.yres,
- panel_info.vl_col, panel_info.vl_row);
+ fb_mode.xres, fb_mode.yres,
+ panel_info.vl_col, panel_info.vl_row);
lcd_enabled = 0;
return;
}
default:
printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
- end - vm, vm, color_depth);
+ end - vm, vm,
+ color_depth);
}
bpp_set = 1;
} else if (!refresh_set) {
}
if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
- p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
+ p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
lcd_enabled = 0;
return;
}
(p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1000);
debug("Pixel clock set to %lu.%03lu MHz\n",
- PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
+ PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
if (p != &fb_mode) {
int ret;
debug("Creating new display-timing node from '%s'\n",
- video_mode);
+ video_mode);
ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
if (ret)
printf("Failed to create new display-timing node from '%s': %d\n",
- video_mode, ret);
+ video_mode, ret);
}
gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
- ARRAY_SIZE(stk5_lcd_pads));
+ ARRAY_SIZE(stk5_lcd_pads));
debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
- color_depth, refresh);
+ color_depth, refresh);
if (karo_load_splashimage(0) == 0) {
char vmode[128];
/* setup env variable for mxsfb display driver */
snprintf(vmode, sizeof(vmode),
- "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
- p->xres, p->yres, p->left_margin, p->right_margin,
- p->upper_margin, p->lower_margin, p->hsync_len,
- p->vsync_len, p->sync, p->pixclock, color_depth);
+ "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
+ p->xres, p->yres, p->left_margin, p->right_margin,
+ p->upper_margin, p->lower_margin, p->hsync_len,
+ p->vsync_len, p->sync, p->pixclock, color_depth);
setenv("videomode", vmode);
debug("Initializing LCD controller\n");
printf("Failed to request stk5_gpios: %d\n", ret);
return;
}
+
imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
if (getenv_yesno("jtag_enable") != 0) {
/* true if unset or set to one of: 'yYtT1' */
imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
}
+
debug("%s@%d: \n", __func__, __LINE__);
}
tx6ul_mmc_init();
ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
- "Flexcan Transceiver");
+ "Flexcan Transceiver");
if (ret) {
printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
return;
}
imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
- TX6UL_GPIO_OUT_PAD_CTRL);
+ TX6UL_GPIO_OUT_PAD_CTRL);
+}
+
+static void tx_tester_board_init(void)
+{
+ int ret;
+
+ setenv("video_mode", NULL);
+ setenv("touchpanel", NULL);
+ if (getenv("eth1addr") && !getenv("ethprime"))
+ setenv("ethprime", "FEC1");
+
+ ret = gpio_request_array(tx_tester_gpios, ARRAY_SIZE(tx_tester_gpios));
+ if (ret) {
+ printf("Failed to request TX-Tester GPIOs: %d\n", ret);
+ return;
+ }
+ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+
+ if (wrsr & WRSR_TOUT)
+ gpio_set_value(IMX_GPIO_NR(5, 4), 1);
+
+ if (getenv_yesno("jtag_enable") != 0) {
+ /* true if unset or set to one of: 'yYtT1' */
+ imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads,
+ ARRAY_SIZE(stk5_jtag_pads));
+ }
+
+ gpio_set_value(IMX_GPIO_NR(3, 8), 1);
}
static void tx6ul_set_cpu_clock(void)
if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
printf("%s detected; skipping cpu clock change\n",
- (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
+ (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
return;
}
if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
cpu_clk = mxc_get_clock(MXC_ARM_CLK);
printf("CPU clock set to %lu.%03lu MHz\n",
- cpu_clk / 1000000, cpu_clk / 1000 % 1000);
+ cpu_clk / 1000000, cpu_clk / 1000 % 1000);
} else {
printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
}
if (otg_mode && strcmp(otg_mode, "host") == 0) {
printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
- otg_mode, baseboard);
+ otg_mode, baseboard);
setenv("otg_mode", "none");
}
stk5v5_board_init();
if (otg_mode && strcmp(otg_mode, "host") == 0) {
printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
- otg_mode, baseboard);
+ otg_mode, baseboard);
setenv("otg_mode", "none");
}
stk5_board_init();
+ } else if (strncmp(baseboard, "tx-tester-", 10) == 0) {
+ const char *otg_mode = getenv("otg_mode");
+
+ if (!otg_mode || strcmp(otg_mode, "none") != 0)
+ setenv("otg_mode", "device");
+ tx_tester_board_init();
} else {
printf("WARNING: Unsupported baseboard: '%s'\n",
baseboard);
+ printf("Reboot with <CTRL-C> pressed to fix this\n");
if (!had_ctrlc())
return -EINVAL;
}
#define ETH_ALEN 6
#endif
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ unsigned int mac0, mac1, mac2;
+ unsigned int __maybe_unused fuse3_override, fuse4_override;
+
+ memset(mac, 0, 6);
+
+ switch (dev_id) {
+ case 0:
+ if (fuse_read(4, 2, &mac0)) {
+ printf("Failed to read MAC0 fuse\n");
+ return;
+ }
+ if (fuse_read(4, 3, &mac1)) {
+ printf("Failed to read MAC1 fuse\n");
+ return;
+ }
+ mac[0] = mac1 >> 8;
+ mac[1] = mac1;
+ mac[2] = mac0 >> 24;
+ mac[3] = mac0 >> 16;
+ mac[4] = mac0 >> 8;
+ mac[5] = mac0;
+ break;
+
+ case 1:
+ if (fuse_read(4, 3, &mac1)) {
+ printf("Failed to read MAC1 fuse\n");
+ return;
+ }
+ debug("read %08x from fuse 3\n", mac1);
+ if (fuse_read(4, 4, &mac2)) {
+ printf("Failed to read MAC2 fuse\n");
+ return;
+ }
+ debug("read %08x from fuse 4\n", mac2);
+ mac[0] = mac2 >> 24;
+ mac[1] = mac2 >> 16;
+ mac[2] = mac2 >> 8;
+ mac[3] = mac2;
+ mac[4] = mac1 >> 24;
+ mac[5] = mac1 >> 16;
+ break;
+
+ default:
+ return;
+ }
+ debug("%s@%d: Done %d %pM\n", __func__, __LINE__, dev_id, mac);
+}
+
static void tx6ul_init_mac(void)
{
u8 mac[ETH_ALEN];
if (getenv("eth1addr"))
return;
imx_get_mac_from_fuse(1, mac);
- eth_setenv_enetaddr("eth1addr", mac);
+ if (is_valid_ethaddr(mac))
+ eth_setenv_enetaddr("eth1addr", mac);
}
int board_eth_init(bd_t *bis)
udelay(22000);
imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
- ARRAY_SIZE(tx6ul_enet1_pads));
+ ARRAY_SIZE(tx6ul_enet1_pads));
/* Deassert RESET to the external phys */
gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
}
if (getenv("eth1addr")) {
ret = gpio_request_array(tx6ul_fec2_gpios,
- ARRAY_SIZE(tx6ul_fec2_gpios));
+ ARRAY_SIZE(tx6ul_fec2_gpios));
if (ret < 0) {
printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
}
imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
- ARRAY_SIZE(tx6ul_enet2_pads));
+ ARRAY_SIZE(tx6ul_enet2_pads));
writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
- ARRAY_SIZE(tx6ul_touchpanels));
+ ARRAY_SIZE(tx6ul_touchpanels));
karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
karo_fdt_fixup_flexcan(blob, stk5_v5);
- karo_fdt_update_fb_mode(blob, video_mode);
+ karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
return 0;
}
projects / karo-tx-uboot.git / blobdiff