PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST)
#define TX6UL_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
+ PAD_CTL_ODE | \
PAD_CTL_HYS | \
PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_34ohm | \
PAD_CTL_SRE_FAST)
+#define TX6UL_I2C_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
+ PAD_CTL_HYS | \
+ PAD_CTL_DSE_34ohm | \
+ PAD_CTL_SPEED_MED)
#define TX6UL_ENET_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | \
PAD_CTL_PUS_100K_UP | \
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
};
-static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
+static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
/* internal I2C */
MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
- MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
- PAD_CTL_ODE), /* I2C SCL */
+ TX6UL_I2C_PAD_CTRL, /* I2C SCL */
+ MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
+ TX6UL_I2C_PAD_CTRL, /* I2C SDA */
+};
+
+static const iomux_v3_cfg_t const tx6ul_i2c_gpio_pads[] = {
+ /* internal I2C set up for I2C bus recovery */
+ MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
+ TX6UL_I2C_PAD_CTRL, /* I2C SCL */
MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
- MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
- PAD_CTL_ODE), /* I2C SDA */
+ TX6UL_I2C_PAD_CTRL, /* I2C SDA */
};
static const struct gpio const tx6ul_gpios[] = {
/* run with default environment */
#if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
-static void tx6_i2c_recover(void)
+#define SCL_BANK (TX6UL_I2C1_SCL_GPIO / 32)
+#define SDA_BANK (TX6UL_I2C1_SDA_GPIO / 32)
+#define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
+#define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
+
+static void * const gpio_ports[] = {
+ (void *)GPIO1_BASE_ADDR,
+ (void *)GPIO2_BASE_ADDR,
+ (void *)GPIO3_BASE_ADDR,
+ (void *)GPIO4_BASE_ADDR,
+ (void *)GPIO5_BASE_ADDR,
+};
+
+static void tx6ul_i2c_recover(void)
{
int i;
int bad = 0;
-#define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
-#define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
-#define I2C_GPIO_BASE (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
+ struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
+ struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
- if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
- (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
+ if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
+ (readl(&sda_regs->gpio_psr) & SDA_BIT))
return;
debug("Clearing I2C bus\n");
- if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
+ if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
printf("I2C SCL stuck LOW\n");
bad++;
- writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
- I2C_GPIO_BASE + GPIO_DR);
- writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
- I2C_GPIO_BASE + GPIO_DIR);
+ setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
+ setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
+
+ imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
+ MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
}
- if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
+ if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
printf("I2C SDA stuck LOW\n");
bad++;
- writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
- I2C_GPIO_BASE + GPIO_DIR);
- writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
- I2C_GPIO_BASE + GPIO_DR);
- writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
- I2C_GPIO_BASE + GPIO_DIR);
+ clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
+ setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
+ setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
- imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
- ARRAY_SIZE(tx6_i2c_gpio_pads));
- udelay(10);
+ imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_gpio_pads,
+ ARRAY_SIZE(tx6ul_i2c_gpio_pads));
+
+ udelay(5);
for (i = 0; i < 18; i++) {
- u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
+ u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
- writel(reg, I2C_GPIO_BASE + GPIO_DR);
- udelay(10);
- if (reg & SCL_BIT &&
- readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
+ writel(reg, &scl_regs->gpio_dr);
+ udelay(5);
+ if (reg & SCL_BIT) {
+ if (readl(&sda_regs->gpio_psr) & SDA_BIT)
+ break;
+ if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
+ break;
break;
+ }
}
}
if (bad) {
- u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
+ bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
+ bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
- if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
+ if (scl && sda) {
printf("I2C bus recovery succeeded\n");
} else {
- printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
- SCL_BIT | SDA_BIT);
+ printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
+ scl, sda);
}
+ imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
+ ARRAY_SIZE(tx6ul_i2c_pads));
}
}
#else
-static inline void tx6_i2c_recover(void)
+static inline void tx6ul_i2c_recover(void)
{
}
#endif
#ifdef CONFIG_MX6_TEMPERATURE_HOT
check_cpu_temperature(1);
#endif
- tx6_i2c_recover();
+ tx6ul_i2c_recover();
return 0;
}
}
#ifndef CONFIG_MX6_TEMPERATURE_HOT
-static bool tx6_temp_check_enabled = true;
+static bool tx6ul_temp_check_enabled = true;
#else
-#define tx6_temp_check_enabled 0
+#define tx6ul_temp_check_enabled 0
#endif
static inline u8 tx6ul_mem_suffix(void)
static struct pmic_regs rn5t567_regs[] = {
{ RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
- { RN5T567_DC2CTL, DC2_DC2DIS, },
+ { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
{ RN5T567_DC1DAC, VDD_CORE_VAL, },
{ RN5T567_DC3DAC, VDD_DDR_VAL, },
{ RN5T567_DC4DAC, VDD_HIGH_VAL, },
{ RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
};
-static int pmic_addr __maybe_unused = 0x33;
+static int pmic_addr = 0x33;
#endif
int board_init(void)
else
printf("<CTRL-C> detected; safeboot enabled\n");
#ifndef CONFIG_MX6_TEMPERATURE_HOT
- tx6_temp_check_enabled = false;
+ tx6ul_temp_check_enabled = false;
#endif
return 0;
}
}
#ifdef CONFIG_FSL_ESDHC
-#define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \
+#define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST)
};
#endif
-static struct tx6_esdhc_cfg {
+static struct tx6ul_esdhc_cfg {
const iomux_v3_cfg_t *pads;
int num_pads;
enum mxc_clock clkid;
},
};
-static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
+static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
{
- return container_of(cfg, struct tx6_esdhc_cfg, cfg);
+ return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
}
int board_mmc_getcd(struct mmc *mmc)
{
- struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
+ struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
if (cfg->cd_gpio < 0)
return 1;
#endif
for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
struct mmc *mmc;
- struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
+ struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
int ret;
cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
static inline int calc_blink_rate(void)
{
- if (!tx6_temp_check_enabled)
+ if (!tx6ul_temp_check_enabled)
return CONFIG_SYS_HZ;
return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
.vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
};
-static struct fb_videomode tx6_fb_modes[] = {
+static struct fb_videomode tx6ul_fb_modes[] = {
#ifndef CONFIG_SYS_LVDS_IF
{
/* Standard VGA timing */
const char *vm;
unsigned long val;
int refresh = 60;
- struct fb_videomode *p = &tx6_fb_modes[0];
+ struct fb_videomode *p = &tx6ul_fb_modes[0];
struct fb_videomode fb_mode;
int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
printf("Invalid video mode: %s\n", getenv("video_mode"));
lcd_enabled = 0;
printf("Supported video modes are:");
- for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
+ for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
printf(" %s", p->name);
}
printf("\n");
#endif /* CONFIG_LCD */
#ifndef CONFIG_ENV_IS_IN_MMC
-static void tx6_mmc_init(void)
+static void tx6ul_mmc_init(void)
{
puts("MMC: ");
if (board_mmc_init(gd->bd) < 0)
print_mmc_devices(',');
}
#else
-static inline void tx6_mmc_init(void)
+static inline void tx6ul_mmc_init(void)
{
}
#endif
debug("%s@%d: \n", __func__, __LINE__);
stk5_board_init();
debug("%s@%d: \n", __func__, __LINE__);
- tx6_mmc_init();
+ tx6ul_mmc_init();
}
static void stk5v5_board_init(void)
int ret;
stk5_board_init();
- tx6_mmc_init();
+ tx6ul_mmc_init();
ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
"Flexcan Transceiver");
env_cleanup();
- if (tx6_temp_check_enabled)
+ if (tx6ul_temp_check_enabled)
check_cpu_temperature(1);
tx6ul_set_cpu_clock();
#define ETH_ALEN 6
#endif
-static void tx6_init_mac(void)
+static void tx6ul_init_mac(void)
{
u8 mac[ETH_ALEN];
const char *baseboard = getenv("baseboard");
{
int ret;
- tx6_init_mac();
+ tx6ul_init_mac();
/* delay at least 21ms for the PHY internal POR signal to deassert */
udelay(22000);
#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
#endif
-static const char *tx6_touchpanels[] = {
+static const char *tx6ul_touchpanels[] = {
"ti,tsc2007",
"edt,edt-ft5x06",
"eeti,egalax_ts",
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
- karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
- ARRAY_SIZE(tx6_touchpanels));
+ karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
+ ARRAY_SIZE(tx6ul_touchpanels));
karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
karo_fdt_fixup_flexcan(blob, stk5_v5);
projects / karo-tx-uboot.git / blobdiff