u32 cpurev = get_cpu_rev();
char *cpu_str = "?";
- switch ((cpurev >> 12) & 0xff) {
- case MXC_CPU_MX6SL:
+ if (is_cpu_type(MXC_CPU_MX6SL))
cpu_str = "SL";
- break;
- case MXC_CPU_MX6DL:
+ else if (is_cpu_type(MXC_CPU_MX6DL))
cpu_str = "DL";
- break;
- case MXC_CPU_MX6SOLO:
+ else if (is_cpu_type(MXC_CPU_MX6SOLO))
cpu_str = "SOLO";
- break;
- case MXC_CPU_MX6Q:
+ else if (is_cpu_type(MXC_CPU_MX6Q))
cpu_str = "Q";
- break;
- case MXC_CPU_MX6UL:
+ else if (is_cpu_type(MXC_CPU_MX6UL))
cpu_str = "UL";
- break;
- }
printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
cpu_str,
/* TSC200x PEN IRQ */
MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
-#if 0
+
/* EDT-FT5x06 Polytouch panel */
- MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
- MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
- MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
+ MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
+ MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
+ MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
/* USBH1 */
- MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
- MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
+ MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
+ MX6_PAD_GPIO1_IO03__USB_OTG2_OC | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
+
/* USBOTG */
- MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
- MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
- MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
-#endif
+ MX6_PAD_UART3_CTS_B__GPIO1_IO26 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
+ MX6_PAD_UART3_RTS_B__GPIO1_IO27 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
};
static const struct gpio stk5_gpios[] = {
{ TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
- { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
- { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
- { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
- { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
- { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+ { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
+ { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
};
#ifdef CONFIG_LCD
-static u16 tx6_cmap[256];
vidinfo_t panel_info = {
/* set to max. size supported by SoC */
.vl_col = 4096,
.vl_row = 1024,
.vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
- .cmap = tx6_cmap,
};
static struct fb_videomode tx6_fb_modes[] = {
printf("WARNING: Unsupported STK5 board rev.: %s\n",
baseboard + 4);
}
+ } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
+ const char *otg_mode = getenv("otg_mode");
+
+ if (otg_mode && strcmp(otg_mode, "host") == 0) {
+ printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
+ otg_mode, baseboard);
+ setenv("otg_mode", "none");
+ }
+ stk5_board_init();
} else {
printf("WARNING: Unsupported baseboard: '%s'\n",
baseboard);