MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1, 0x00000015)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0, 0x0000f0b9)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1, 0x0000f0b9)
- /* ENET_REF_CLK */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK, 0x00000014)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK, 0x000000b1)
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK, 0x00000014)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK, 0x000000b1)
- MXC_DCD_ITEM(IOMUXC_ENET1_REF_CLK1_SELECT_INPUT, 2)
- MXC_DCD_ITEM(IOMUXC_ENET2_REF_CLK2_SELECT_INPUT, 2)
- /* ETN PHY nRST */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6, 0x00000015)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6, 0x000010b0)
- /* ETN PHY Power */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5, 0x00000015)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5, 0x000010b0)
-#ifndef CONFIG_TX6_EMMC
+#ifdef CONFIG_TX6_NAND
/* switch NFC clock to 99MHz */
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR)
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
#endif
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
-
+ /* switch LCDIF clk source to PLL5 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00011150) /* default: 0x00029150 */
MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */
/* enable all relevant clocks... */
#else
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(1)) /* default: 0x00fc3003 USDHC1 */
#endif
- MXC_DCD_ITEM(IOMUXC_GPR1, 0x00020000) /* default: 0x0f400005 ENET1_TX_CLK output */
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(0x020c80b0, 0)