.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
PHY_EN_DYN_PWRDN,
};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ return (serial_tstc() && serial_getc() == 'c');
+}
+#endif
+
#endif
/*
*/
void s_init(void)
{
+ /*
+ * Save the boot parameters passed from romcode.
+ * We cannot delay the saving further than this,
+ * to prevent overwrites.
+ */
+#ifdef CONFIG_SPL_BUILD
+ save_omap_boot_params();
+#endif
+
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_bone_lt())
- config_ddr(303, MT41K256M16HA125E_IOCTRL_VALUE,
+ config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
eth_setenv_enetaddr("ethaddr", mac_addr);
}
+#ifdef CONFIG_DRIVER_TI_CPSW
if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
+#endif
/*
*