Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

[karo-tx-uboot.git] / drivers / block / systemace.c

diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index dfaab528bf4cb914087fbe59173adb86022c376d..bf29cbbb7a838b4db49b323a9db06942a07fc1ea 100644 (file)
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -20,7 +20,7 @@
 
 /*
  * The Xilinx SystemACE chip support is activated by defining
- * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE
+ * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE
  * to set the base address of the device. This code currently
  * assumes that the chip is connected via a byte-wide bus.
  *
@@ -47,31 +47,43 @@
 /*
  * The ace_readw and writew functions read/write 16bit words, but the
  * offset value is the BYTE offset as most used in the Xilinx
- * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined
+ * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined
  * to be the base address for the chip, usually in the local
  * peripheral bus.
  */
-#if (CFG_SYSTEMACE_WIDTH == 8)
+
+static u32 base = CONFIG_SYS_SYSTEMACE_BASE;
+static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH;
+
+static void ace_writew(u16 val, unsigned off)
+{
+       if (width == 8) {
 #if !defined(__BIG_ENDIAN)
-#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \
-                       (readb(CFG_SYSTEMACE_BASE+off+1)))
-#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \
-                             writeb(val, CFG_SYSTEMACE_BASE+off+1);}
+               writeb(val >> 8, base + off);
+               writeb(val, base + off + 1);
 #else
-#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \
-                       (readb(CFG_SYSTEMACE_BASE+off+1)<<8))
-#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \
-                             writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);}
+               writeb(val, base + off);
+               writeb(val >> 8, base + off + 1);
 #endif
+       } else
+               out16(base + off, val);
+}
+
+static u16 ace_readw(unsigned off)
+{
+       if (width == 8) {
+#if !defined(__BIG_ENDIAN)
+               return (readb(base + off) << 8) | readb(base + off + 1);
 #else
-#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off))
-#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val))
+               return readb(base + off) | (readb(base + off + 1) << 8);
 #endif
+       }
 
-/* */
+       return in16(base + off);
+}
 
 static unsigned long systemace_read(int dev, unsigned long start,
-                                   unsigned long blkcnt, void *buffer);
+                                       lbaint_t blkcnt, void *buffer);
 
 static block_dev_desc_t systemace_dev = { 0 };
 
@@ -104,6 +116,7 @@ static void release_cf_lock(void)
        ace_writew((val & 0xffff), 0x18);
 }
 
+#ifdef CONFIG_PARTITIONS
 block_dev_desc_t *systemace_get_dev(int dev)
 {
        /* The first time through this, the systemace_dev object is
@@ -120,7 +133,7 @@ block_dev_desc_t *systemace_get_dev(int dev)
                /*
                 * Ensure the correct bus mode (8/16 bits) gets enabled
                 */
-               ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0);
+               ace_writew(width == 8 ? 0 : 0x0001, 0);
 
                init_part(&systemace_dev);
 
@@ -128,6 +141,7 @@ block_dev_desc_t *systemace_get_dev(int dev)
 
        return &systemace_dev;
 }
+#endif
 
 /*
  * This function is called (by dereferencing the block_read pointer in
@@ -135,7 +149,7 @@ block_dev_desc_t *systemace_get_dev(int dev)
  * number of blocks read. A zero return indicates an error.
  */
 static unsigned long systemace_read(int dev, unsigned long start,
-                                   unsigned long blkcnt, void *buffer)
+                                       lbaint_t blkcnt, void *buffer)
 {
        int retry;
        unsigned blk_countdown;