net: sh-eth: Add support Gigabit of SH7734

[karo-tx-uboot.git] / drivers / net / sh_eth.c

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 27d040125eef311df3d22a03b5024764ca5c65fb..bb57e4d53a03a2c82f326479bdd6893d475456a3 100644 (file)
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -1,8 +1,8 @@
 /*
  * sh_eth.c - Driver for Renesas SH7763's ethernet controler.
  *
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (c) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008, 2011 Renesas Solutions Corp.
+ * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -44,9 +44,9 @@
 #define flush_cache_wback(...)
 #endif
 
-#define SH_ETH_PHY_DELAY 50000
+#define TIMEOUT_CNT 1000
 
-int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
+int sh_eth_send(struct eth_device *dev, void *packet, int len)
 {
        struct sh_eth_dev *eth = dev->priv;
        int port = eth->port, ret = 0, timeout;
@@ -59,7 +59,7 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
        }
 
        /* packet must be a 4 byte boundary */
-       if ((int)packet & (4 - 1)) {
+       if ((int)packet & 3) {
                printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
                ret = -EFAULT;
                goto err;
@@ -80,7 +80,7 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
                outl(EDTRR_TRNS, EDTRR(port));
 
        /* Wait until packet is transmitted */
-       timeout = 1000;
+       timeout = TIMEOUT_CNT;
        while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
                udelay(100);
 
@@ -94,7 +94,6 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
        if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
                port_info->tx_desc_cur = port_info->tx_desc_base;
 
-       return ret;
 err:
        return ret;
 }
@@ -104,15 +103,15 @@ int sh_eth_recv(struct eth_device *dev)
        struct sh_eth_dev *eth = dev->priv;
        int port = eth->port, len = 0;
        struct sh_eth_info *port_info = &eth->port_info[port];
-       volatile u8 *packet;
+       uchar *packet;
 
        /* Check if the rx descriptor is ready */
        if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
                /* Check for errors */
                if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
                        len = port_info->rx_desc_cur->rd1 & 0xffff;
-                       packet = (volatile u8 *)
-                           ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+                       packet = (uchar *)
+                               ADDR_TO_P2(port_info->rx_desc_cur->rd2);
                        NetReceive(packet, len);
                }
 
@@ -136,11 +135,10 @@ int sh_eth_recv(struct eth_device *dev)
        return len;
 }
 
-#define EDMR_INIT_CNT 1000
 static int sh_eth_reset(struct sh_eth_dev *eth)
 {
        int port = eth->port;
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
        int ret = 0, i;
 
        /* Start e-dmac transmitter and receiver */
@@ -148,13 +146,13 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
 
        /* Perform a software reset and wait for it to complete */
        outl(EDMR_SRST, EDMR(port));
-       for (i = 0; i < EDMR_INIT_CNT; i++) {
+       for (i = 0; i < TIMEOUT_CNT ; i++) {
                if (!(inl(EDMR(port)) & EDMR_SRST))
                        break;
                udelay(1000);
        }
 
-       if (i == EDMR_INIT_CNT) {
+       if (i == TIMEOUT_CNT) {
                printf(SHETHER_NAME  ": Software reset timeout\n");
                ret = -EIO;
        }
@@ -210,7 +208,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
        /* Point the controller to the tx descriptor list. Must use physical
           addresses */
        outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
        outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
        outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
        outl(0x01, TDFFR(port));/* Last discriptor bit */
@@ -278,7 +276,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 
        /* Point the controller to the rx descriptor list */
        outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
        outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
        outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
        outl(RDFFR_RDLF, RDFFR(port));
@@ -348,8 +346,9 @@ static int sh_eth_phy_config(struct sh_eth_dev *eth)
        struct eth_device *dev = port_info->dev;
        struct phy_device *phydev;
 
-       phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
-                       port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII);
+       phydev = phy_connect(
+                       miiphy_get_dev_by_name(dev->name),
+                       port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
        port_info->phydev = phydev;
        phy_config(phydev);
 
@@ -371,7 +370,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
        outl(0, TFTR(port));
        outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
        outl(RMCR_RST, RMCR(port));
-#ifndef CONFIG_CPU_SH7757
+#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
        outl(0, RPADIR(port));
 #endif
        outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
@@ -393,15 +392,21 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
        outl(val, MALR(port));
 
        outl(RFLR_RFL_MIN, RFLR(port));
-#ifndef CONFIG_CPU_SH7757
+#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
        outl(0, PIPR(port));
 #endif
+#if !defined(CONFIG_CPU_SH7724)
        outl(APR_AP, APR(port));
        outl(MPR_MP, MPR(port));
-#ifdef CONFIG_CPU_SH7757
-       outl(TPAUSER_UNLIMITED, TPAUSER(port));
-#else
+#endif
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
        outl(TPAUSER_TPAUSE, TPAUSER(port));
+#elif defined(CONFIG_CPU_SH7757)
+       outl(TPAUSER_UNLIMITED, TPAUSER(port));
+#endif
+
+#if defined(CONFIG_CPU_SH7734)
+       outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port));
 #endif
        /* Configure phy */
        ret = sh_eth_phy_config(eth);
@@ -412,33 +417,40 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
        phy = port_info->phydev;
        phy_startup(phy);
 
+       val = 0;
+
        /* Set the transfer speed */
-#ifdef CONFIG_CPU_SH7763
        if (phy->speed == 100) {
                printf(SHETHER_NAME ": 100Base/");
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
                outl(GECMR_100B, GECMR(port));
+#elif defined(CONFIG_CPU_SH7757)
+               outl(1, RTRATE(port));
+#elif defined(CONFIG_CPU_SH7724)
+               val = ECMR_RTM;
+#endif
        } else if (phy->speed == 10) {
                printf(SHETHER_NAME ": 10Base/");
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
                outl(GECMR_10B, GECMR(port));
-       }
-#endif
-#if defined(CONFIG_CPU_SH7757)
-       if (phy->speed == 100) {
-               printf("100Base/");
-               outl(1, RTRATE(port));
-       } else if (phy->speed == 10) {
-               printf("10Base/");
+#elif defined(CONFIG_CPU_SH7757)
                outl(0, RTRATE(port));
+#endif
+       }
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+       else if (phy->speed == 1000) {
+               printf(SHETHER_NAME ": 1000Base/");
+               outl(GECMR_1000B, GECMR(port));
        }
 #endif
 
        /* Check if full duplex mode is supported by the phy */
        if (phy->duplex) {
                printf("Full\n");
-               outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
+               outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
        } else {
                printf("Half\n");
-               outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE),  ECMR(port));
+               outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE),  ECMR(port));
        }
 
        return ret;