/*
* sh_eth.c - Driver for Renesas SH7763's ethernet controler.
*
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (c) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008, 2011 Renesas Solutions Corp.
+ * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
*
* This program is free software; you can redistribute it and/or modify
#include <malloc.h>
#include <net.h>
#include <netdev.h>
+#include <miiphy.h>
#include <asm/errno.h>
#include <asm/io.h>
#ifndef CONFIG_SH_ETHER_PHY_ADDR
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
+#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define flush_cache_wback(addr, len) \
+ dcache_wback_range((u32)addr, (u32)(addr + len - 1))
+#else
+#define flush_cache_wback(...)
+#endif
-#define SH_ETH_PHY_DELAY 50000
-
-/*
- * Bits are written to the PHY serially using the
- * PIR register, just like a bit banger.
- */
-static void sh_eth_mii_write_phy_bits(int port, u32 val, int len)
-{
- int i;
- u32 pir;
-
- /* Bit positions is 1 less than the number of bits */
- for (i = len - 1; i >= 0; i--) {
- /* Write direction, bit to write, clock is low */
- pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
- outl(pir, PIR(port));
- udelay(1);
- /* Write direction, bit to write, clock is high */
- pir = 3 | ((val & 1 << i) ? 1 << 2 : 0);
- outl(pir, PIR(port));
- udelay(1);
- /* Write direction, bit to write, clock is low */
- pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
- outl(pir, PIR(port));
- udelay(1);
- }
-}
-
-static void sh_eth_mii_bus_release(int port)
-{
- /* Read direction, clock is low */
- outl(0, PIR(port));
- udelay(1);
- /* Read direction, clock is high */
- outl(1, PIR(port));
- udelay(1);
- /* Read direction, clock is low */
- outl(0, PIR(port));
- udelay(1);
-}
-
-static void sh_eth_mii_ind_bus_release(int port)
-{
- /* Read direction, clock is low */
- outl(0, PIR(port));
- udelay(1);
-}
-
-static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len)
-{
- int i;
- u32 pir;
-
- *val = 0;
- for (i = len - 1; i >= 0; i--) {
- /* Read direction, clock is high */
- outl(1, PIR(port));
- udelay(1);
- /* Read bit */
- pir = inl(PIR(port));
- *val |= (pir & 8) ? 1 << i : 0;
- /* Read direction, clock is low */
- outl(0, PIR(port));
- udelay(1);
- }
-}
-
-#define PHY_INIT 0xFFFFFFFF
-#define PHY_READ 0x02
-#define PHY_WRITE 0x01
-/*
- * To read a phy register, mii managements frames are sent to the phy.
- * The frames look like this:
- * pre (32 bits): 0xffff ffff
- * st (2 bits): 01
- * op (2bits): 10: read 01: write
- * phyad (5 bits): xxxxx
- * regad (5 bits): xxxxx
- * ta (Bus release):
- * data (16 bits): read data
- */
-static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg)
-{
- u32 val;
-
- /* Sent mii management frame */
- /* pre */
- sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
- /* st (start of frame) */
- sh_eth_mii_write_phy_bits(port, 0x1, 2);
- /* op (code) */
- sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
- /* phy address */
- sh_eth_mii_write_phy_bits(port, phy_addr, 5);
- /* Register to read */
- sh_eth_mii_write_phy_bits(port, reg, 5);
-
- /* Bus release */
- sh_eth_mii_bus_release(port);
-
- /* Read register */
- sh_eth_mii_read_phy_bits(port, &val, 16);
-
- return val;
-}
-
-/*
- * To write a phy register, mii managements frames are sent to the phy.
- * The frames look like this:
- * pre (32 bits): 0xffff ffff
- * st (2 bits): 01
- * op (2bits): 10: read 01: write
- * phyad (5 bits): xxxxx
- * regad (5 bits): xxxxx
- * ta (2 bits): 10
- * data (16 bits): write data
- * idle (Independent bus release)
- */
-static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val)
-{
- /* Sent mii management frame */
- /* pre */
- sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
- /* st (start of frame) */
- sh_eth_mii_write_phy_bits(port, 0x1, 2);
- /* op (code) */
- sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2);
- /* phy address */
- sh_eth_mii_write_phy_bits(port, phy_addr, 5);
- /* Register to read */
- sh_eth_mii_write_phy_bits(port, reg, 5);
- /* ta */
- sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
- /* Write register data */
- sh_eth_mii_write_phy_bits(port, val, 16);
-
- /* Independent bus release */
- sh_eth_mii_ind_bus_release(port);
-}
+#define TIMEOUT_CNT 1000
-int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
+int sh_eth_send(struct eth_device *dev, void *packet, int len)
{
struct sh_eth_dev *eth = dev->priv;
int port = eth->port, ret = 0, timeout;
}
/* packet must be a 4 byte boundary */
- if ((int)packet & (4 - 1)) {
+ if ((int)packet & 3) {
printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
ret = -EFAULT;
goto err;
}
/* Update tx descriptor */
+ flush_cache_wback(packet, len);
port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
port_info->tx_desc_cur->td1 = len << 16;
/* Must preserve the end of descriptor list indication */
outl(EDTRR_TRNS, EDTRR(port));
/* Wait until packet is transmitted */
- timeout = 1000;
+ timeout = TIMEOUT_CNT;
while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
udelay(100);
if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
port_info->tx_desc_cur = port_info->tx_desc_base;
- return ret;
err:
return ret;
}
struct sh_eth_dev *eth = dev->priv;
int port = eth->port, len = 0;
struct sh_eth_info *port_info = ð->port_info[port];
- volatile u8 *packet;
+ uchar *packet;
/* Check if the rx descriptor is ready */
if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
/* Check for errors */
if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
len = port_info->rx_desc_cur->rd1 & 0xffff;
- packet = (volatile u8 *)
- ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+ packet = (uchar *)
+ ADDR_TO_P2(port_info->rx_desc_cur->rd2);
NetReceive(packet, len);
}
return len;
}
-#define EDMR_INIT_CNT 1000
static int sh_eth_reset(struct sh_eth_dev *eth)
{
int port = eth->port;
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
/* Perform a software reset and wait for it to complete */
outl(EDMR_SRST, EDMR(port));
- for (i = 0; i < EDMR_INIT_CNT; i++) {
+ for (i = 0; i < TIMEOUT_CNT ; i++) {
if (!(inl(EDMR(port)) & EDMR_SRST))
break;
udelay(1000);
}
- if (i == EDMR_INIT_CNT) {
+ if (i == TIMEOUT_CNT) {
printf(SHETHER_NAME ": Software reset timeout\n");
ret = -EIO;
}
return ret;
+#else
+ outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
+ udelay(3000);
+ outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
+
+ return 0;
+#endif
}
static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
~(TX_DESC_SIZE - 1));
+ flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
port_info->tx_desc_cur = port_info->tx_desc_base;
/* Point the controller to the tx descriptor list. Must use physical
addresses */
outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
outl(0x01, TDFFR(port));/* Last discriptor bit */
+#endif
err:
return ret;
tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
~(RX_DESC_SIZE - 1));
+ flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
/* Make sure we use a P2 address (non-cacheable) */
port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
/* Point the controller to the rx descriptor list */
outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
outl(RDFFR_RDLF, RDFFR(port));
+#endif
return ret;
static int sh_eth_phy_config(struct sh_eth_dev *eth)
{
- int port = eth->port, timeout, ret = 0;
+ int port = eth->port, ret = 0;
struct sh_eth_info *port_info = ð->port_info[port];
- u32 val;
-
- /* Reset phy */
- sh_eth_mii_write_phy_reg
- (port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET);
- timeout = 10;
- while (timeout--) {
- val = sh_eth_mii_read_phy_reg(port,
- port_info->phy_addr, PHY_CTRL);
- if (!(val & PHY_C_RESET))
- break;
- udelay(SH_ETH_PHY_DELAY);
- }
-
- if (timeout < 0) {
- printf(SHETHER_NAME ": phy reset timeout\n");
- ret = -EIO;
- goto err_tout;
- }
-
- /* Advertise 100/10 baseT full/half duplex */
- sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA,
- (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT));
- /* Autonegotiation, normal operation, full duplex, enable tx */
- sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL,
- (PHY_C_ANEGEN|PHY_C_RANEG));
- /* Wait for autonegotiation to complete */
- timeout = 100;
- while (timeout--) {
- val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
- if (val & PHY_S_ANEGC)
- break;
-
- udelay(SH_ETH_PHY_DELAY);
- }
-
- if (timeout < 0) {
- printf(SHETHER_NAME ": phy auto-negotiation failed\n");
- ret = -ETIMEDOUT;
- goto err_tout;
- }
+ struct eth_device *dev = port_info->dev;
+ struct phy_device *phydev;
- return ret;
+ phydev = phy_connect(
+ miiphy_get_dev_by_name(dev->name),
+ port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
+ port_info->phydev = phydev;
+ phy_config(phydev);
-err_tout:
return ret;
}
static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
{
int port = eth->port, ret = 0;
- u32 val, phy_status;
+ u32 val;
struct sh_eth_info *port_info = ð->port_info[port];
struct eth_device *dev = port_info->dev;
+ struct phy_device *phy;
/* Configure e-dmac registers */
outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
outl(0, TFTR(port));
outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
outl(RMCR_RST, RMCR(port));
+#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
outl(0, RPADIR(port));
+#endif
outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
/* Configure e-mac registers */
+#if defined(CONFIG_CPU_SH7757)
+ outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
+ ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port));
+#else
outl(0, ECSIPR(port));
+#endif
/* Set Mac address */
val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
outl(val, MALR(port));
outl(RFLR_RFL_MIN, RFLR(port));
+#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
outl(0, PIPR(port));
+#endif
+#if !defined(CONFIG_CPU_SH7724)
outl(APR_AP, APR(port));
outl(MPR_MP, MPR(port));
+#endif
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(TPAUSER_TPAUSE, TPAUSER(port));
+#elif defined(CONFIG_CPU_SH7757)
+ outl(TPAUSER_UNLIMITED, TPAUSER(port));
+#endif
+#if defined(CONFIG_CPU_SH7734)
+ outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port));
+#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
if (ret) {
- printf(SHETHER_NAME ":i phy config timeout\n");
+ printf(SHETHER_NAME ": phy config timeout\n");
goto err_phy_cfg;
}
- /* Read phy status to finish configuring the e-mac */
- phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
+ phy = port_info->phydev;
+ phy_startup(phy);
+
+ val = 0;
/* Set the transfer speed */
- if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
+ if (phy->speed == 100) {
printf(SHETHER_NAME ": 100Base/");
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(GECMR_100B, GECMR(port));
- } else {
+#elif defined(CONFIG_CPU_SH7757)
+ outl(1, RTRATE(port));
+#elif defined(CONFIG_CPU_SH7724)
+ val = ECMR_RTM;
+#endif
+ } else if (phy->speed == 10) {
printf(SHETHER_NAME ": 10Base/");
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(GECMR_10B, GECMR(port));
+#elif defined(CONFIG_CPU_SH7757)
+ outl(0, RTRATE(port));
+#endif
+ }
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+ else if (phy->speed == 1000) {
+ printf(SHETHER_NAME ": 1000Base/");
+ outl(GECMR_1000B, GECMR(port));
}
+#endif
/* Check if full duplex mode is supported by the phy */
- if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) {
+ if (phy->duplex) {
printf("Full\n");
- outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
+ outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
} else {
printf("Half\n");
- outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
+ outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
}
return ret;
/* Register Device to EtherNet subsystem */
eth_register(dev);
+ bb_miiphy_buses[0].priv = eth;
+ miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
+
if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
puts("Please set MAC address\n");
printf(SHETHER_NAME ": Failed\n");
return ret;
}
+
+/******* for bb_miiphy *******/
+static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
+{
+ return 0;
+}
+
+static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ int port = eth->port;
+
+ outl(inl(PIR(port)) | PIR_MMD, PIR(port));
+
+ return 0;
+}
+
+static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ int port = eth->port;
+
+ outl(inl(PIR(port)) & ~PIR_MMD, PIR(port));
+
+ return 0;
+}
+
+static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ int port = eth->port;
+
+ if (v)
+ outl(inl(PIR(port)) | PIR_MDO, PIR(port));
+ else
+ outl(inl(PIR(port)) & ~PIR_MDO, PIR(port));
+
+ return 0;
+}
+
+static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ int port = eth->port;
+
+ *v = (inl(PIR(port)) & PIR_MDI) >> 3;
+
+ return 0;
+}
+
+static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ int port = eth->port;
+
+ if (v)
+ outl(inl(PIR(port)) | PIR_MDC, PIR(port));
+ else
+ outl(inl(PIR(port)) & ~PIR_MDC, PIR(port));
+
+ return 0;
+}
+
+static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(10);
+
+ return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = "sh_eth",
+ .init = sh_eth_bb_init,
+ .mdio_active = sh_eth_bb_mdio_active,
+ .mdio_tristate = sh_eth_bb_mdio_tristate,
+ .set_mdio = sh_eth_bb_set_mdio,
+ .get_mdio = sh_eth_bb_get_mdio,
+ .set_mdc = sh_eth_bb_set_mdc,
+ .delay = sh_eth_bb_delay,
+ }
+};
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
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