/*
- * sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler.
+ * sh_eth.h - Driver for Renesas SuperH ethernet controler.
*
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (c) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008, 2011 Renesas Solutions Corp.
+ * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
*
* This program is free software; you can redistribute it and/or modify
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
+#include <netdev.h>
#include <asm/types.h>
#define SHETHER_NAME "sh_eth"
#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
/* The ethernet controller needs to use physical addresses */
+#if defined(CONFIG_SH_32BIT)
+#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
+#else
#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
+#endif
/* Number of supported ports */
#define MAX_PORT_NUM 2
#define TX_DESC_PADDING 4
#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
-/* Tx descriptor. We always use 4 bytes of padding */
+/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
volatile u32 td0;
u32 td1;
u32 padding;
};
-struct port_info_s {
+struct sh_eth_info {
struct tx_desc_s *tx_desc_malloc;
struct tx_desc_s *tx_desc_base;
struct tx_desc_s *tx_desc_cur;
u8 *rx_buf_base;
u8 mac_addr[6];
u8 phy_addr;
+ struct eth_device *dev;
+ struct phy_device *phydev;
};
-struct dev_info_s {
+struct sh_eth_dev {
int port;
- struct port_info_s port_info[MAX_PORT_NUM];
+ struct sh_eth_info port_info[MAX_PORT_NUM];
};
/* Register Address */
+#ifdef CONFIG_CPU_SH7763
#define BASE_IO_ADDR 0xfee00000
#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
+#elif defined(CONFIG_CPU_SH7757)
+#define BASE_IO_ADDR 0xfef00000
+
+#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
+#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020)
+
+#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
+#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008)
+#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
+#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028)
+#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
+#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
+#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048)
+#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050)
+#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058)
+#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070)
+#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100)
+#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108)
+#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118)
+#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120)
+#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154)
+#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158)
+#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164)
+#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
+#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
+#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
+
+#elif defined(CONFIG_CPU_SH7724)
+#define BASE_IO_ADDR 0xA4600000
+
+#define TDLAR(port) (BASE_IO_ADDR + 0x0018)
+#define RDLAR(port) (BASE_IO_ADDR + 0x0020)
+
+#define EDMR(port) (BASE_IO_ADDR + 0x0000)
+#define EDTRR(port) (BASE_IO_ADDR + 0x0008)
+#define EDRRR(port) (BASE_IO_ADDR + 0x0010)
+#define EESR(port) (BASE_IO_ADDR + 0x0028)
+#define EESIPR(port) (BASE_IO_ADDR + 0x0030)
+#define TRSCER(port) (BASE_IO_ADDR + 0x0038)
+#define TFTR(port) (BASE_IO_ADDR + 0x0048)
+#define FDR(port) (BASE_IO_ADDR + 0x0050)
+#define RMCR(port) (BASE_IO_ADDR + 0x0058)
+#define FCFTR(port) (BASE_IO_ADDR + 0x0070)
+#define ECMR(port) (BASE_IO_ADDR + 0x0100)
+#define RFLR(port) (BASE_IO_ADDR + 0x0108)
+#define ECSIPR(port) (BASE_IO_ADDR + 0x0118)
+#define PIR(port) (BASE_IO_ADDR + 0x0120)
+#define APR(port) (BASE_IO_ADDR + 0x0154)
+#define MPR(port) (BASE_IO_ADDR + 0x0158)
+#define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
+#define MAHR(port) (BASE_IO_ADDR + 0x01c0)
+#define MALR(port) (BASE_IO_ADDR + 0x01c8)
+
+#elif defined(CONFIG_CPU_SH7734)
+#define BASE_IO_ADDR 0xFEE00000
+
+#define EDSR(port) (BASE_IO_ADDR)
+
+#define TDLAR(port) (BASE_IO_ADDR + 0x0010)
+#define TDFAR(port) (BASE_IO_ADDR + 0x0014)
+#define TDFXR(port) (BASE_IO_ADDR + 0x0018)
+#define TDFFR(port) (BASE_IO_ADDR + 0x001c)
+#define RDLAR(port) (BASE_IO_ADDR + 0x0030)
+#define RDFAR(port) (BASE_IO_ADDR + 0x0034)
+#define RDFXR(port) (BASE_IO_ADDR + 0x0038)
+#define RDFFR(port) (BASE_IO_ADDR + 0x003c)
+
+#define EDMR(port) (BASE_IO_ADDR + 0x0400)
+#define EDTRR(port) (BASE_IO_ADDR + 0x0408)
+#define EDRRR(port) (BASE_IO_ADDR + 0x0410)
+#define EESR(port) (BASE_IO_ADDR + 0x0428)
+#define EESIPR(port) (BASE_IO_ADDR + 0x0430)
+#define TRSCER(port) (BASE_IO_ADDR + 0x0438)
+#define TFTR(port) (BASE_IO_ADDR + 0x0448)
+#define FDR(port) (BASE_IO_ADDR + 0x0450)
+#define RMCR(port) (BASE_IO_ADDR + 0x0458)
+#define RPADIR(port) (BASE_IO_ADDR + 0x0460)
+#define FCFTR(port) (BASE_IO_ADDR + 0x0468)
+#define ECMR(port) (BASE_IO_ADDR + 0x0500)
+#define RFLR(port) (BASE_IO_ADDR + 0x0508)
+#define ECSIPR(port) (BASE_IO_ADDR + 0x0518)
+#define PIR(port) (BASE_IO_ADDR + 0x0520)
+#define PIPR(port) (BASE_IO_ADDR + 0x052c)
+#define APR(port) (BASE_IO_ADDR + 0x0554)
+#define MPR(port) (BASE_IO_ADDR + 0x0558)
+#define TPAUSER(port) (BASE_IO_ADDR + 0x0564)
+#define GECMR(port) (BASE_IO_ADDR + 0x05b0)
+#define MAHR(port) (BASE_IO_ADDR + 0x05C0)
+#define MALR(port) (BASE_IO_ADDR + 0x05C8)
+#define RMII_MII(port) (BASE_IO_ADDR + 0x0790)
+
+#endif
+
/*
* Register's bits
* Copy from Linux driver source code
*/
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
/* EDSR */
enum EDSR_BIT {
EDSR_ENT = 0x01, EDSR_ENR = 0x02,
/* EDMR */
enum DMAC_M_BIT {
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
-#ifdef CONFIG_CPU_SH7763
- EDMR_SRST = 0x03,
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+ EDMR_SRST = 0x03, /* Receive/Send reset */
+ EMDR_DESC_R = 0x30, /* Descriptor reserve size */
+ EDMR_EL = 0x40, /* Litte endian */
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7724)
+ EDMR_SRST = 0x01,
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
#else /* CONFIG_CPU_SH7763 */
/* EDTRR */
enum DMAC_T_BIT {
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
EDTRR_TRNS = 0x03,
#else
EDTRR_TRNS = 0x01,
/* GECMR */
enum GECMR_BIT {
- GECMR_1000B = 0x01, GECMR_100B = 0x40, GECMR_10B = 0x00,
+ GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
};
/* EDRRR*/
/* EESR */
enum EESR_BIT {
-#ifndef CONFIG_CPU_SH7763
+
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
EESR_TWB = 0x40000000,
#else
EESR_TWB = 0xC0000000,
#endif
EESR_TABT = 0x04000000,
EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
-#ifndef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
EESR_ADE = 0x00800000,
#endif
EESR_ECI = 0x00400000,
EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
-#ifndef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757)
EESR_CND = 0x00000800,
#endif
EESR_DLC = 0x00000400,
};
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
# define TX_CHECK (EESR_TC1 | EESR_FTC)
# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
/* Transfer descriptor bit */
enum TD_STS_BIT {
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
+ || defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7734)
TD_TACT = 0x80000000,
#else
TD_TACT = 0x7fffffff,
enum RECV_RST_BIT { RMCR_RST = 0x01, };
/* ECMR */
enum FELIC_MODE_BIT {
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
ECMR_RZPF = 0x00100000,
#endif
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
ECMR_PRM = 0x00000001,
+#ifdef CONFIG_CPU_SH7724
+ ECMR_RTM = 0x00000010,
+#endif
+
};
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
ECMR_TXF | ECMR_MCT)
+#elif CONFIG_CPU_SH7757
+#define ECMR_CHG_DM (ECMR_ZPF)
+#elif CONFIG_CPU_SH7724
+#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
#else
-#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT)
+#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
#endif
/* ECSR */
enum ECSR_STATUS_BIT {
-#ifndef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
#endif
ECSR_LCHNG = 0x04,
ECSR_MPD = 0x02, ECSR_ICD = 0x01,
};
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
#else
# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
/* ECSIPR */
enum ECSIPR_STATUS_MASK_BIT {
-#ifndef CONFIG_CPU_SH7763
- ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
-#endif
+#if defined(CONFIG_CPU_SH7724)
+ ECSIPR_PSRTOIP = 0x10,
+ ECSIPR_LCHNGIP = 0x04,
+ ECSIPR_ICDIP = 0x01,
+#elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+ ECSIPR_PSRTOIP = 0x10,
+ ECSIPR_PHYIP = 0x08,
ECSIPR_LCHNGIP = 0x04,
- ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
+ ECSIPR_MPDIP = 0x02,
+ ECSIPR_ICDIP = 0x01,
+#endif
};
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
#else
# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
/* APR */
enum APR_BIT {
+#ifdef CONFIG_CPU_SH7757
+ APR_AP = 0x00000001,
+#else
APR_AP = 0x00000004,
+#endif
};
/* MPR */
enum MPR_BIT {
+#ifdef CONFIG_CPU_SH7757
+ MPR_MP = 0x00000001,
+#else
MPR_MP = 0x00000006,
+#endif
};
/* TRSCER */
RPADIR_PADR = 0x0003f,
};
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
# define RPADIR_INIT (0x00)
#else
# define RPADIR_INIT (RPADIR_PADS1)
enum FIFO_SIZE_BIT {
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
};
-
-enum PHY_OFFSETS {
- PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
- PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
- PHY_16 = 16,
-};
-
-/* PHY_CTRL */
-enum PHY_CTRL_BIT {
- PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
- PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
- PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
-};
-#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
-
-/* PHY_STAT */
-enum PHY_STAT_BIT {
- PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
- PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
- PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
- PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
-};
-
-/* PHY_ANA */
-enum PHY_ANA_BIT {
- PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
- PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
- PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
- PHY_A_SEL = 0x001e,
- PHY_A_EXT = 0x0001,
-};
-
-/* PHY_ANL */
-enum PHY_ANL_BIT {
- PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
- PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
- PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
- PHY_L_SEL = 0x001f,
-};
-
-/* PHY_ANE */
-enum PHY_ANE_BIT {
- PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
- PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
-};
-
-/* DM9161 */
-enum PHY_16_BIT {
- PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
- PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
- PHY_16_TXselect = 0x0400,
- PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
- PHY_16_Force100LNK = 0x0080,
- PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
- PHY_16_RPDCTR_EN = 0x0010,
- PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
- PHY_16_Sleepmode = 0x0002,
- PHY_16_RemoteLoopOut = 0x0001,
-};
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