unsigned long value;
struct lcd_dma_desc *desc;
struct atmel_hlcd_regs *regs;
+ u32 clk_pol;
if (!has_lcdc())
return; /* No lcdc */
regs = panel_info.mmio;
+ clk_pol = panel_info.vl_clk_pol ? LCDC_LCDCFG0_CLKPOL : 0;
/* Disable DISP signal */
lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
| LCDC_LCDCFG0_CGDISHEO
| LCDC_LCDCFG0_CGDISOVR1
| LCDC_LCDCFG0_CGDISBASE
- | panel_info.vl_clk_pol
- | LCDC_LCDCFG0_CLKSEL);
+ | LCDC_LCDCFG0_CLKSEL
+ | clk_pol);
} else {
lcdc_writel(®s->lcdc_lcdcfg0,
| LCDC_LCDCFG0_CGDISHEO
| LCDC_LCDCFG0_CGDISOVR1
| LCDC_LCDCFG0_CGDISBASE
- | panel_info.vl_clk_pol);
+ | clk_pol);
}
/* Initialize control register 5 */