mx31pdk: add CONFIG_SPL_LIBGENERIC_SUPPORT

[karo-tx-uboot.git] / include / configs / mx31pdk.h

diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index b272674f820e8a193603dc39aff5418aee84c7d3..82ea4fa92ebea1278f9b2268353f12f961dce189 100644 (file)
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -45,7 +45,17 @@
 
 #define CONFIG_MACH_TYPE       MACH_TYPE_MX31_3DS
 
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET      "u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT    "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE    2048
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE   0x87dc0000
+#define CONFIG_SYS_TEXT_BASE   0x87e00000
+
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 
@@ -60,7 +70,6 @@
 
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE   UART1_BASE
-#define CONFIG_HW_WATCHDOG
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_HARD_SPI
@@ -69,9 +78,9 @@
 #define CONFIG_DEFAULT_SPI_MODE        (SPI_MODE_0 | SPI_CS_HIGH)
 
 /* PMIC Controller */
-#define CONFIG_PMIC
-#define CONFIG_PMIC_SPI
-#define CONFIG_PMIC_FSL
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
 #define CONFIG_FSL_PMIC_BUS    1
 #define CONFIG_FSL_PMIC_CS     2
 #define CONFIG_FSL_PMIC_CLK    1000000
@@ -106,7 +115,7 @@
 
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_BOOTDELAY       3
+#define CONFIG_BOOTDELAY       1
 
 #define        CONFIG_EXTRA_ENV_SETTINGS                                       \
        "bootargs_base=setenv bootargs console=ttymxc0,115200\0"        \
@@ -115,7 +124,7 @@
        "bootcmd=run bootcmd_net\0"                                     \
        "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "     \
                "tftpboot 0x81000000 uImage-mx31; bootm\0"              \
-       "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; "               \
+       "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; "           \
                "nand erase 0x0 0x40000; "                              \
                "nand write 0x81000000 0x0 0x40000\0"
 
@@ -162,7 +171,7 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - \
                                                GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_SYS_INIT_RAM_ADDR + \
-                                               CONFIG_SYS_GBL_DATA_OFFSET)
+                                               CONFIG_SYS_INIT_RAM_SIZE)
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
@@ -188,10 +197,10 @@
 /* NAND configuration for the NAND_SPL */
 
 /* Start copying real U-boot from the second page */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x800
-#define CONFIG_SYS_NAND_U_BOOT_SIZE    0x30000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    0x3f800
 /* Load U-Boot to this address */
-#define CONFIG_SYS_NAND_U_BOOT_DST     0x87f00000
+#define CONFIG_SYS_NAND_U_BOOT_DST     CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 
 #define CONFIG_SYS_NAND_PAGE_SIZE      0x800
@@ -203,11 +212,11 @@
 
 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
 #define CCM_CCMR_SETUP         0x074B0BF5
-#define CCM_PDR0_SETUP_532MHZ  (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
-                                PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |     \
-                                PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |     \
-                                PDR0_MCU_PODF(0))
-#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |   \
+#define CCM_PDR0_SETUP_532MHZ  (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
+                                PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
+                                PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
+                                PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
                                 PLL_MFN(12))
 
 #define ESDMISC_MDDR_SETUP     0x00000004