*/
#define CONFIG_NR_DRAM_BANKS 0x1 /* # of SDRAM banks */
#define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */
-#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
-#define PHYS_SDRAM_1_WIDTH CONFIG_SYS_SDRAM_BUS_WIDTH
-#elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32)
-#define PHYS_SDRAM_1_WIDTH 32
+#ifndef CONFIG_SYS_SDRAM_BUS_WIDTH
+#if defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32)
+#define CONFIG_SYS_SDRAM_BUS_WIDTH 32
#elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_16)
-#define PHYS_SDRAM_1_WIDTH 16
+#define CONFIG_SYS_SDRAM_BUS_WIDTH 16
#else
-#define PHYS_SDRAM_1_WIDTH 64
+#define CONFIG_SYS_SDRAM_BUS_WIDTH 64
#endif
-#define PHYS_SDRAM_1_SIZE (SZ_512M / 32 * PHYS_SDRAM_1_WIDTH)
+#endif /* CONFIG_SYS_SDRAM_BUS_WIDTH */
+#define PHYS_SDRAM_1_SIZE (SZ_512M / 32 * CONFIG_SYS_SDRAM_BUS_WIDTH)
#ifdef CONFIG_SOC_MX6Q
#define CONFIG_SYS_SDRAM_CLK 528
#else