X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=README;h=0a0f528af117e94f86918078b23b7ec8c5561f96;hp=1e63f048efe6fb6a9e004e530832c80bb3520fe8;hb=1f359e3611c55d9cfae88dafce04db1833033bd0;hpb=3e1b36bd584228b0a8070c8b63351aefda652523

diff --git a/README b/README
index 1e63f048ef..0a0f528af1 100644
--- a/README
+++ b/README
@@ -959,6 +959,7 @@ The following options need to be configured:
 		CONFIG_CMD_BMP		* BMP support
 		CONFIG_CMD_BSP		* Board specific commands
 		CONFIG_CMD_BOOTD	  bootd
+		CONFIG_CMD_BOOTI	* ARM64 Linux kernel Image support
 		CONFIG_CMD_CACHE	* icache, dcache
 		CONFIG_CMD_CLK   	* clock command support
 		CONFIG_CMD_CONSOLE	  coninfo
@@ -1378,6 +1379,10 @@ The following options need to be configured:
 			CONFIG_SH_ETHER_CACHE_WRITEBACK
 			If this option is set, the driver enables cache flush.
 
+- PWM Support:
+		CONFIG_PWM_IMX
+		Support for PWM modul on the imx6.
+
 - TPM Support:
 		CONFIG_TPM
 		Support TPM devices.
@@ -2949,6 +2954,17 @@ CBFS (Coreboot Filesystem) support
 		memories can be connected with a given cs line.
 		currently Xilinx Zynq qspi support these type of connections.
 
+		CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
+		enable the W#/Vpp signal to disable writing to the status
+		register on ST MICRON flashes like the N25Q128.
+		The status register write enable/disable bit, combined with
+		the W#/VPP signal provides hardware data protection for the
+		device as follows: When the enable/disable bit is set to 1,
+		and the W#/VPP signal is driven LOW, the status register
+		nonvolatile bits become read-only and the WRITE STATUS REGISTER
+		operation will not execute. The only way to exit this
+		hardware-protected mode is to drive W#/VPP HIGH.
+
 - SystemACE Support:
 		CONFIG_SYSTEMACE