X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farm926ejs%2Fmxs%2Fspl_mem_init.c;h=bd72f36e2132911bc7ff6544c8f1279853f1e322;hp=3902406441e9df700c6c9606a047b4b5d022303f;hb=ef10f5faa7a37f6a7936ba840c4a308c924baff4;hpb=286a88cf34bcfec4a1051b5ee3553277e6c31e2e diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 3902406441..bd72f36e21 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -4,23 +4,7 @@ * Copyright (C) 2011 Marek Vasut * on behalf of DENX Software Engineering GmbH * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -36,7 +20,7 @@ static uint32_t dram_vals[] = { /* * i.MX28 DDR2 at 200MHz */ -#if defined(CONFIG_MX28) +#if defined(CONFIG_SOC_MX28) 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -89,7 +73,7 @@ static uint32_t dram_vals[] = { /* * i.MX23 DDR at 133MHz */ -#elif defined(CONFIG_MX23) +#elif defined(CONFIG_SOC_MX23) 0x01010001, 0x00010100, 0x01000101, 0x00000001, 0x00000101, 0x00000000, 0x00010000, 0x01000001, 0x00000000, 0x00000001, 0x07000200, 0x00070202, @@ -108,15 +92,18 @@ static uint32_t dram_vals[] = { __weak void mxs_adjust_memory_params(uint32_t *dram_vals) { + debug("SPL: Using default SDRAM parameters\n"); } -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 static void initialize_dram_values(void) { int i; + debug("SPL: Setting mx28 board specific SDRAM parameters\n"); mxs_adjust_memory_params(dram_vals); + debug("SPL: Applying SDRAM parameters\n"); for (i = 0; i < ARRAY_SIZE(dram_vals); i++) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); } @@ -125,6 +112,7 @@ static void initialize_dram_values(void) { int i; + debug("SPL: Setting mx23 board specific SDRAM parameters\n"); mxs_adjust_memory_params(dram_vals); /* @@ -136,6 +124,7 @@ static void initialize_dram_values(void) * HW_DRAM_CTL8 is setup as the last element. * So skip the initialization of these HW_DRAM_CTL registers. */ + debug("SPL: Applying SDRAM parameters\n"); for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { if (i == 8 || i == 27 || i == 28 || i == 35) continue; @@ -154,14 +143,16 @@ static void mxs_mem_init_clock(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ const unsigned char divider = 33; -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ const unsigned char divider = 21; #endif + debug("SPL: Initialising FRAC0\n"); + /* Gate EMI clock */ writeb(CLKCTRL_FRAC_CLKGATE, &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); @@ -174,18 +165,18 @@ static void mxs_mem_init_clock(void) writeb(CLKCTRL_FRAC_CLKGATE, &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); - early_delay(11000); /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), &clkctrl_regs->hw_clkctrl_emi); + while (readl(&clkctrl_regs->hw_clkctrl_emi) & CLKCTRL_EMI_BUSY_REF_EMI) + ; /* Unbypass EMI */ writel(CLKCTRL_CLKSEQ_BYPASS_EMI, &clkctrl_regs->hw_clkctrl_clkseq_clr); - - early_delay(10000); + debug("SPL: FRAC0 Initialised\n"); } static void mxs_mem_setup_cpu_and_hbus(void) @@ -193,6 +184,8 @@ static void mxs_mem_setup_cpu_and_hbus(void) struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + debug("SPL: Setting CPU and HBUS clock frequencies\n"); + /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz * and ungate CPU clock */ writeb(19 & CLKCTRL_FRAC_FRAC_MASK, @@ -203,74 +196,77 @@ static void mxs_mem_setup_cpu_and_hbus(void) &clkctrl_regs->hw_clkctrl_clkseq_set); /* HBUS = 151MHz */ - writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); - writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, - &clkctrl_regs->hw_clkctrl_hbus_clr); - - early_delay(10000); + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_hbus, + CLKCTRL_HBUS_DIV_MASK, + 3 << CLKCTRL_HBUS_DIV_OFFSET); + while (readl(&clkctrl_regs->hw_clkctrl_hbus) & CLKCTRL_HBUS_ASM_BUSY) + ; /* CPU clock divider = 1 */ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, - CLKCTRL_CPU_DIV_CPU_MASK, 1); + CLKCTRL_CPU_DIV_CPU_MASK, + 1 << CLKCTRL_CPU_DIV_CPU_OFFSET); + while (readl(&clkctrl_regs->hw_clkctrl_cpu) & CLKCTRL_CPU_BUSY_REF_CPU) + ; /* Disable CPU bypass */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU, &clkctrl_regs->hw_clkctrl_clkseq_clr); - - early_delay(15000); } -static void mxs_mem_setup_vdda(void) +static void data_abort_memdetect_handler(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | - (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | - POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, - &power_regs->hw_power_vddactrl); + asm volatile("subs pc, lr, #4"); } uint32_t mxs_mem_get_size(void) { uint32_t sz, da; uint32_t *vt = (uint32_t *)0x20; - /* The following is "subs pc, r14, #4", used as return from DABT. */ - const uint32_t data_abort_memdetect_handler = 0xe25ef004; + unsigned long cr; + + /* move vector table to low memory */ + asm volatile( + "mrc p15, 0, %0, c1, c0, 0\n" + "bic r7, %0, #(1 << 13)\n" + "mcr p15, 0, r7, c1, c0, 0\n" + : "=r"(cr) : : "r7"); /* Replace the DABT handler. */ da = vt[4]; - vt[4] = data_abort_memdetect_handler; + vt[4] = (uint32_t)data_abort_memdetect_handler; sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); /* Restore the old DABT handler. */ vt[4] = da; + asm volatile("mcr p15, 0, %0, c1, c0, 0\n" : : "r"(cr)); return sz; } -#ifdef CONFIG_MX23 +#ifdef CONFIG_SOC_MX23 static void mx23_mem_setup_vddmem(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; - writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) | - POWER_VDDMEMCTRL_ENABLE_ILIMIT | - POWER_VDDMEMCTRL_ENABLE_LINREG | - POWER_VDDMEMCTRL_PULLDOWN_ACTIVE, - &power_regs->hw_power_vddmemctrl); + debug("SPL: Setting mx23 VDDMEM\n"); - early_delay(10000); + /* We must wait before and after disabling the current limiter! */ + udelay(10000); + + clrbits_le32(&power_regs->hw_power_vddmemctrl, + POWER_VDDMEMCTRL_ENABLE_ILIMIT); + + udelay(10000); - writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) | - POWER_VDDMEMCTRL_ENABLE_LINREG, - &power_regs->hw_power_vddmemctrl); } static void mx23_mem_init(void) { + debug("SPL: Initialising mx23 SDRAM Controller\n"); + /* * Reset/ungate the EMI block. This is essential, otherwise the system * suffers from memory instability. This thing is mx23 specific and is @@ -293,23 +289,31 @@ static void mx23_mem_init(void) setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); - early_delay(20000); + + /* Wait for EMI_STAT bit DRAM_HALTED */ + for (;;) { + if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1))) + break; + udelay(1000); + } /* Adjust EMI port priority. */ clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); - early_delay(20000); + udelay(20000); setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); } #endif -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 static void mx28_mem_init(void) { struct mxs_pinctrl_regs *pinctrl_regs = (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; + debug("SPL: Initialising mx28 SDRAM Controller\n"); + /* Set DDR2 mode */ writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); @@ -337,19 +341,15 @@ static void mx28_mem_init(void) void mxs_mem_init(void) { - early_delay(11000); + udelay(11000); mxs_mem_init_clock(); - mxs_mem_setup_vdda(); - -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) mx23_mem_init(); -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) mx28_mem_init(); #endif - early_delay(10000); - mxs_mem_setup_cpu_and_hbus(); }