X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farm926ejs%2Fmxs%2Fspl_mem_init.c;h=bd72f36e2132911bc7ff6544c8f1279853f1e322;hp=44cf84d5a9822d09840c61a0b130720f8ba831f9;hb=ef10f5faa7a37f6a7936ba840c4a308c924baff4;hpb=ac880a37757934db1ef765bd43721231575747bf

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 44cf84d5a9..bd72f36e21 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -20,7 +20,7 @@ static uint32_t dram_vals[] = {
 /*
  * i.MX28 DDR2 at 200MHz
  */
-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)
 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -73,7 +73,7 @@ static uint32_t dram_vals[] = {
 /*
  * i.MX23 DDR at 133MHz
  */
-#elif defined(CONFIG_MX23)
+#elif defined(CONFIG_SOC_MX23)
 	0x01010001, 0x00010100, 0x01000101, 0x00000001,
 	0x00000101, 0x00000000, 0x00010000, 0x01000001,
 	0x00000000, 0x00000001, 0x07000200, 0x00070202,
@@ -92,15 +92,18 @@ static uint32_t dram_vals[] = {
 
 __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
+	debug("SPL: Using default SDRAM parameters\n");
 }
 
-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28
 static void initialize_dram_values(void)
 {
 	int i;
 
+	debug("SPL: Setting mx28 board specific SDRAM parameters\n");
 	mxs_adjust_memory_params(dram_vals);
 
+	debug("SPL: Applying SDRAM parameters\n");
 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
 		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
@@ -109,6 +112,7 @@ static void initialize_dram_values(void)
 {
 	int i;
 
+	debug("SPL: Setting mx23 board specific SDRAM parameters\n");
 	mxs_adjust_memory_params(dram_vals);
 
 	/*
@@ -120,6 +124,7 @@ static void initialize_dram_values(void)
 	 * HW_DRAM_CTL8 is setup as the last element.
 	 * So skip the initialization of these HW_DRAM_CTL registers.
 	 */
+	debug("SPL: Applying SDRAM parameters\n");
 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
 		if (i == 8 || i == 27 || i == 28 || i == 35)
 			continue;
@@ -138,14 +143,16 @@ static void mxs_mem_init_clock(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)
 	/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
 	const unsigned char divider = 33;
-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)
 	/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
 	const unsigned char divider = 21;
 #endif
 
+	debug("SPL: Initialising FRAC0\n");
+
 	/* Gate EMI clock */
 	writeb(CLKCTRL_FRAC_CLKGATE,
 		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
@@ -169,6 +176,7 @@ static void mxs_mem_init_clock(void)
 	/* Unbypass EMI */
 	writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
 		&clkctrl_regs->hw_clkctrl_clkseq_clr);
+	debug("SPL: FRAC0 Initialised\n");
 }
 
 static void mxs_mem_setup_cpu_and_hbus(void)
@@ -176,6 +184,8 @@ static void mxs_mem_setup_cpu_and_hbus(void)
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
+	debug("SPL: Setting CPU and HBUS clock frequencies\n");
+
 	/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
 	 * and ungate CPU clock */
 	writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
@@ -204,7 +214,7 @@ static void mxs_mem_setup_cpu_and_hbus(void)
 		&clkctrl_regs->hw_clkctrl_clkseq_clr);
 }
 
-void data_abort_memdetect_handler(void)
+static void data_abort_memdetect_handler(void)
 {
 	asm volatile("subs pc, lr, #4");
 }
@@ -235,19 +245,28 @@ uint32_t mxs_mem_get_size(void)
 	return sz;
 }
 
-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23
 static void mx23_mem_setup_vddmem(void)
 {
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;
 
+	debug("SPL: Setting mx23 VDDMEM\n");
+
+	/* We must wait before and after disabling the current limiter! */
+	udelay(10000);
+
 	clrbits_le32(&power_regs->hw_power_vddmemctrl,
 		POWER_VDDMEMCTRL_ENABLE_ILIMIT);
 
+	udelay(10000);
+
 }
 
 static void mx23_mem_init(void)
 {
+	debug("SPL: Initialising mx23 SDRAM Controller\n");
+
 	/*
 	 * Reset/ungate the EMI block. This is essential, otherwise the system
 	 * suffers from memory instability. This thing is mx23 specific and is
@@ -270,23 +289,31 @@ static void mx23_mem_init(void)
 	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
 
 	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
-	early_delay(20000);
+
+	/* Wait for EMI_STAT bit DRAM_HALTED */
+	for (;;) {
+		if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
+			break;
+		udelay(1000);
+	}
 
 	/* Adjust EMI port priority. */
 	clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
-	early_delay(20000);
+	udelay(20000);
 
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
 }
 #endif
 
-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28
 static void mx28_mem_init(void)
 {
 	struct mxs_pinctrl_regs *pinctrl_regs =
 		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
 
+	debug("SPL: Initialising mx28 SDRAM Controller\n");
+
 	/* Set DDR2 mode */
 	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
 		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
@@ -314,13 +341,13 @@ static void mx28_mem_init(void)
 
 void mxs_mem_init(void)
 {
-	early_delay(11000);
+	udelay(11000);
 
 	mxs_mem_init_clock();
 
-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)
 	mx23_mem_init();
-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)
 	mx28_mem_init();
 #endif