X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fam33xx%2Fboard.c;h=9a69b6ccfac4ff6197d8b6a214bbd8279a8fc587;hp=05a2d28ba16594ab255ded558ffa61c71bc97659;hb=87acf194a298f65a40c659036a5e413613d458e6;hpb=6a0d803c7c9eeee24f579b764eb4bc51ed79eb5e

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 05a2d28ba1..9a69b6ccfa 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -32,14 +32,19 @@
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
 #include <asm/omap_musb.h>
+#include <asm/davinci_rtc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct gpio_bank gpio_bank_am33xx[4] = {
+static const struct gpio_bank gpio_bank_am33xx[] = {
 	{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+#ifdef CONFIG_AM43XX
+	{ (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+#endif
 };
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
@@ -137,30 +142,34 @@ int arch_misc_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 /*
  * This function is the place to do per-board things such as ramp up the
  * MPU clock frequency.
  */
 __weak void am33xx_spl_board_init(void)
 {
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 static void rtc32k_enable(void)
 {
-	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 
 	/*
 	 * Unlock the RTC's registers.  For more details please see the
 	 * RTC_SS section of the TRM.  In order to unlock we need to
 	 * write these specific values (keys) in this order.
 	 */
-	writel(0x83e70b13, &rtc->kick0r);
-	writel(0x95a4f1e0, &rtc->kick1r);
+	writel(RTC_KICK0R_WE, &rtc->kick0r);
+	writel(RTC_KICK1R_WE, &rtc->kick1r);
 
 	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
 	writel((1 << 3) | (1 << 6), &rtc->osc);
 }
+#endif
 
 static void uart_soft_reset(void)
 {
@@ -191,7 +200,6 @@ static void watchdog_disable(void)
 	while (readl(&wdtimer->wdtwwps) != 0x0)
 		;
 }
-#endif
 
 void s_init(void)
 {
@@ -211,26 +219,35 @@ void s_init(void)
 #ifdef CONFIG_SPL_BUILD
 	save_omap_boot_params();
 #endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 	watchdog_disable();
 	timer_init();
 	set_uart_mux_conf();
 	setup_clocks_for_console();
 	uart_soft_reset();
-#endif
-#ifdef CONFIG_NOR_BOOT
+#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
 	gd->baudrate = CONFIG_BAUDRATE;
 	serial_init();
 	gd->have_console = 1;
-#else
+#elif defined(CONFIG_SPL_BUILD)
 	gd = &gdata;
 	preloader_console_init();
 #endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 	prcm_init();
 	set_mux_conf_regs();
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
+#endif
+#ifdef CONFIG_SPL_BUILD
 	sdram_init();
 #endif
 }
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif /* !CONFIG_SYS_DCACHE_OFF */