X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fam33xx%2Femif4.c;h=a7a3e88cd75b3d31f63311f3beebb175f2ea838f;hp=b2d7c0d95621495f3ad3c6c8beb3281217681f3d;hb=87acf194a298f65a40c659036a5e413613d458e6;hpb=8f082d78fafd94db3f21b503794e0875d3331e53

diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index b2d7c0d956..a7a3e88cd7 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -5,15 +5,7 @@
  *
  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -29,6 +21,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	sdram_init();
+#endif
+
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
 			(void *)CONFIG_SYS_SDRAM_BASE,
@@ -43,137 +39,98 @@ void dram_init_banksize(void)
 }
 
 
-#ifdef CONFIG_SPL_BUILD
-static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_TI81XX
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+				(struct dmm_lisa_map_regs *)DMM_BASE;
+#endif
+#ifndef CONFIG_TI816X
+static struct vtp_reg *vtpreg[2] = {
+				(struct vtp_reg *)VTP0_CTRL_ADDR,
+				(struct vtp_reg *)VTP1_CTRL_ADDR};
+#endif
+#ifdef CONFIG_AM33XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+#endif
+#ifdef CONFIG_AM43XX
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+static struct cm_device_inst *cm_device =
+				(struct cm_device_inst *)CM_DEVICE_INST;
+#endif
+
+#ifdef CONFIG_TI81XX
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+	enable_dmm_clocks();
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
+}
+#endif
 
-static const struct ddr_data ddr2_data = {
-	.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
-				|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
-	.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
-				|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
-	.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
-				|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
-	.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
-				|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
-	.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
-				|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
-	.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
-				|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
-	.datauserank0delay = DDR2_PHY_RANK0_DELAY,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
-	.cmd0csratio = DDR2_RATIO,
-	.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
-	.cmd0iclkout = DDR2_INVERT_CLKOUT,
-
-	.cmd1csratio = DDR2_RATIO,
-	.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
-	.cmd1iclkout = DDR2_INVERT_CLKOUT,
-
-	.cmd2csratio = DDR2_RATIO,
-	.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
-	.cmd2iclkout = DDR2_INVERT_CLKOUT,
-};
-
-static const struct emif_regs ddr2_emif_reg_data = {
-	.sdram_config = DDR2_EMIF_SDCFG,
-	.ref_ctrl = DDR2_EMIF_SDREF,
-	.sdram_tim1 = DDR2_EMIF_TIM1,
-	.sdram_tim2 = DDR2_EMIF_TIM2,
-	.sdram_tim3 = DDR2_EMIF_TIM3,
-	.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
-};
-
-static const struct ddr_data ddr3_data = {
-	.datardsratio0 = DDR3_RD_DQS,
-	.datawdsratio0 = DDR3_WR_DQS,
-	.datafwsratio0 = DDR3_PHY_FIFO_WE,
-	.datawrsratio0 = DDR3_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = DDR3_RATIO,
-	.cmd0dldiff = DDR3_DLL_LOCK_DIFF,
-	.cmd0iclkout = DDR3_INVERT_CLKOUT,
-
-	.cmd1csratio = DDR3_RATIO,
-	.cmd1dldiff = DDR3_DLL_LOCK_DIFF,
-	.cmd1iclkout = DDR3_INVERT_CLKOUT,
-
-	.cmd2csratio = DDR3_RATIO,
-	.cmd2dldiff = DDR3_DLL_LOCK_DIFF,
-	.cmd2iclkout = DDR3_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = DDR3_EMIF_SDCFG,
-	.ref_ctrl = DDR3_EMIF_SDREF,
-	.sdram_tim1 = DDR3_EMIF_TIM1,
-	.sdram_tim2 = DDR3_EMIF_TIM2,
-	.sdram_tim3 = DDR3_EMIF_TIM3,
-	.zq_config = DDR3_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
-};
-
-static void config_vtp(void)
+#ifndef CONFIG_TI816X
+static void config_vtp(int nr)
 {
-	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
-			&vtpreg->vtp0ctrlreg);
-	writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
-			&vtpreg->vtp0ctrlreg);
-	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
-			&vtpreg->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
+			&vtpreg[nr]->vtp0ctrlreg);
 
 	/* Poll for READY */
-	while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
+	while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
 			VTP_CTRL_READY)
 		;
 }
+#endif
 
-void config_ddr(short ddr_type)
+void __weak ddr_pll_config(unsigned int ddrpll_m)
 {
-	int ddr_pll, ioctrl_val;
-	const struct emif_regs *emif_regs;
-	const struct ddr_data *ddr_data;
-	const struct cmd_control *cmd_ctrl_data;
-
-	if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
-		ddr_pll = 266;
-		cmd_ctrl_data = &ddr2_cmd_ctrl_data;
-		ddr_data = &ddr2_data;
-		ioctrl_val = DDR2_IOCTRL_VALUE;
-		emif_regs = &ddr2_emif_reg_data;
-	} else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
-		ddr_pll = 303;
-		cmd_ctrl_data = &ddr3_cmd_ctrl_data;
-		ddr_data = &ddr3_data;
-		ioctrl_val = DDR3_IOCTRL_VALUE;
-		emif_regs = &ddr3_emif_reg_data;
-	} else {
-		puts("Unknown memory type");
-		hang();
-	}
-
-	enable_emif_clocks();
-	ddr_pll_config(ddr_pll);
-	config_vtp();
-	config_cmd_ctrl(cmd_ctrl_data);
-
-	config_ddr_data(0, ddr_data);
-	config_ddr_data(1, ddr_data);
-
-	config_io_ctrl(ioctrl_val);
+}
+
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
+		const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs, int nr)
+{
+	ddr_pll_config(pll);
+#ifndef CONFIG_TI816X
+	config_vtp(nr);
+#endif
+	config_cmd_ctrl(ctrl, nr);
+
+	config_ddr_data(data, nr);
+#ifdef CONFIG_AM33XX
+	config_io_ctrl(ioregs);
 
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+#endif
+#ifdef CONFIG_AM43XX
+	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
+	while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
+		;
+	writel(0x80000000, &ddrctrl->ddrioctrl);
+
+	config_io_ctrl(ioregs);
+
+	/* Set CKE to be controlled by EMIF/DDR PHY */
+	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+#endif
 
 	/* Program EMIF instance */
-	config_ddr_phy(emif_regs);
-	set_sdram_timings(emif_regs);
-	config_sdram(emif_regs);
+	config_ddr_phy(regs, nr);
+	set_sdram_timings(regs, nr);
+	if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
+		config_sdram_emif4d5(regs, nr);
+	else
+		config_sdram(regs, nr);
 }
 #endif